



Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
An overview of exception handling in nios ii, a flexible embedded processor architecture. Exceptions are transfer of control away from the normal flow of execution due to internal or external events that require immediate attention. The steps taken by the processor when an exception occurs, returning from an exception, and the process to determine the cause of exceptions. It also discusses the behavior of pio interrupts and timer interrupts, as well as the interrupt controller and jtag uart.
Typology: Study notes
1 / 5
This page cannot be seen from the preview
Don't miss anything!




1
Caused by an event, either internal or external to the processor Requires immediate attention
During eret execution ctl1 is copied to ctl Transfer the execution to the address in ea register
ea contains the address of the instruction after the point where the exception was generated pc+ For software trap and unimplemented instructions, this is correct address Hardware interrupt exceptions must resume execution from the interrupted instruction The exception handler must subtract 4 from ea
3
mul, muli, mulxss, mulxsu, mulxuu, div, divu Start of system memory + 0x 4
irq0 through irq31, an unique input for each interrupt service irq0 has the highest priority ctl0, ctl1, ctl3, and ctl4 are involved 0: disable processor external interrupt 1: enable procesor external interrupt Enable/disable specify interrupt (local) Who asserted interrupt?
7
8
9