Nios II Exception Handling: An Overview, Study notes of Microprocessors

An overview of exception handling in nios ii, a flexible embedded processor architecture. Exceptions are transfer of control away from the normal flow of execution due to internal or external events that require immediate attention. The steps taken by the processor when an exception occurs, returning from an exception, and the process to determine the cause of exceptions. It also discusses the behavior of pio interrupts and timer interrupts, as well as the interrupt controller and jtag uart.

Typology: Study notes

Pre 2010

Uploaded on 09/17/2009

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Exception
An exception is a transfer of control away from a
program’s normal flow of execution
Caused by an event, either internal or external to the
processor
Requires immediate attention
An exception causes the Nios II processor to take
the following steps:
1. Copies the contents of status (ctl0) register to
estatus (ctl1), saving the processor’s pre-exception
status
2. Clears PIE bit of status register (ctl0) to disable external
processor interrupts
3. Write the address of the instruction after (PC+4) the
exception to the ea (r29) register
4. Transfers execution to the address of the exception
handler that determines the cause
2
Returning from an Exception
eret is used to resume execution to the pre-
exception address
During eret execution
ctl1 is copied to ctl0
Transfer the execution to the address in ea register
Be careful with return address!
ea contains the address of the instruction after the point
where the exception was generated
pc+4
For software trap and unimplemented instructions, this is
correct address
Hardware interrupt exceptions must resume execution from
the interrupted instruction
The exception handler must subtract 4 from ea
pf3
pf4
pf5

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1

Exception

 An exception is a transfer of control away from a

program’s normal flow of execution

 Caused by an event, either internal or external to the processor  Requires immediate attention

 An exception causes the Nios II processor to take

the following steps:

  1. Copies the contents of status (ctl0) register to estatus (ctl1), saving the processor’s pre-exception status
  2. Clears PIE bit of status register (ctl0) to disable external processor interrupts
  3. Write the address of the instruction after (PC+4) the exception to the ea (r29) register
  4. Transfers execution to the address of the exception handler that determines the cause 2

Returning from an Exception

 eret is used to resume execution to the pre-

exception address

 During eret execution  ctl1 is copied to ctl  Transfer the execution to the address in ea register

 Be careful with return address!

 ea contains the address of the instruction after the point where the exception was generated  pc+  For software trap and unimplemented instructions, this is correct address  Hardware interrupt exceptions must resume execution from the interrupted instruction  The exception handler must subtract 4 from ea

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Process to Determine

the Cause of Exception

mul, muli, mulxss, mulxsu, mulxuu, div, divu Start of system memory + 0x 4

Interrupt Controller

 Nios II architecture supports 32 level sensitive

external hardware interrupts

 irq0 through irq31, an unique input for each interrupt service  irq0 has the highest priority  ctl0, ctl1, ctl3, and ctl4 are involved 0: disable processor external interrupt 1: enable procesor external interrupt Enable/disable specify interrupt (local) Who asserted interrupt?

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Timer Interrupt Behavior

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Jtag Uart Block Diagram

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Jtag Uart Register Map