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Cork Institute of Technology
Bachelor of Engineering in Electronic Engineering Stage 3 / Summer 2005 Page 1 of 6
Bachelor of Engineering in Electronic Engineering – Award
(National Diploma in Engineering in Electronic Engineering – Award)
(NFQ - Level 7)
Summer 2005
Electronic Engineering
(Time: 3 Hours)
Answer any 5 questions – 20 marks each. Maximum available marks is 100.
Examiners: Mr. Patrick Collins Mr. Jason Berry Dr. Ronan O’Dubhghaill
p=10 -12^ , n=10 -9^ , μ=10 -6^ ,m=10 -3^ , k=10 3 , M=10 6
Q1. An AD741 has the following specifications: At 25°C the input offset voltage is VIO = 5mV , the input bias current is I (^) B = 100nA and the input offset current is I (^) IO = 9nA. ∆V (^) IO /∆T = 15μV/°C , ∆I (^) B /∆T = 700pA/°C. AOL = 106dB. The unity gain bandwidth is UGB = 1.2MHz. The slew rate is SR = 0.5 V/μs.
(a) Draw the frequency response of the magnitude of the open loop gain. Clearly identify the break frequency , the unity gain bandwidth and the slope of the roll-off. [ 4 marks ]
(b) The AD741 is configured as a non-inverting amplifier. The amplifier is required to have a closed loop bandwidth ( fCL ) of at least 20kHz. If the feedback resistor ( Rf ) = 47kΩ then work out the range of the other resistor ( R1 ). [ 4 marks ]
(c) If R1=1kΩ , then what is the maximum value of a sine wave at 5kHz that can applied before slew rate limiting starts to take place? [ 4 marks ]
(d) If R1=1kΩ then what is the maximum possible output error voltage due to input offset voltage and input bias current effects at 25°C? If a balance resistor is used to reduce the output error voltage then what should this resistor value be and what will be the percentage reduction in the original error voltage? [ 4 marks ]
(e) If the temperature rises to 55°C then what is the new maximum possible output error voltage ( with no balance resistor )? [ 4 marks ]
Q2.
(a) For the circuit in Fig 1 derive an expression for Vout in terms of (i) Vin1 and Vin (ii) ECM and EDM where E (^) DM=Vin1–Vin2 and E (^) CM is the common mode input voltage.
Show how , by letting certain resistor values be equal , the amplifier can function as a difference amplifier whose gain can be controlled using resistor ratios. (^) [ 8 marks ]
(b) The amplifier is built with the following values : R1=1005Ω , R2=2000Ω , R3=2000Ω , R4=10100Ω , R5=1000Ω.
If Vin1 = 2.75V and Vin2 = 2.25V then calculate : (i) The portion of the output voltage caused by the common mode input voltage. (ii) The portion of the output voltage caused by the difference mode input voltage. (iii) The total output voltage. (iv) The CMRR of the amplifier. [ 10 marks ]
(c) What is the particular advantage of this difference amplifier configuration? [ 2 marks ]
VIN
VOUT
R
VIN
R
R
R
R
FIGURE 1.
(a) Draw the circuit diagram of a Buck converter. Derive an expression for Vout in terms of the input supply voltage ( VS ) and the duty cycle of the switching element. State any assumptions you make. Include the equivalent circuits when the switch is closed and when the switch is open in your derivation. [ 8 marks ]
(b) Design a buck converter that will produce 5V from a 9V source. Design for continuous inductor current. The output ripple must be no more than 50mV peak-to-peak. Assume ideal components. Assume that the load is a 10Ω resistor. [ 10 marks ]
(c) Find the maximum current flowing through the inductor in your design in part (b). [ 2 marks ]
Q5.
Vin
Vout
RC
VCC
R (^1)
R 2 R (^) E C (^) E RL
C (^) IN
C (^) OUT
R (^) S
FIGURE 3.
For the circuit shown in Fig 3 , Vcc = 15V , RS = 600Ω , R 1 = 18kΩ , R 2 = 22kΩ , RC = 1.8kΩ , RE = 2.7kΩ , RL = 2.7kΩ , CIN = 2.2μF , CE = 10μF and COUT = 4.7μF. The transistor has β = 100 , CBC = 2pF and CBE = 4pF. Calculate : (a) the 3 low cutoff frequencies [ 9 marks ] (b) the input Miller capacitance [ 3 marks ] (c) the output Miller capacitance [ 2 marks ] (d) the 2 high cutoff frequencies. [ 6 marks ] Q6.
R (^) D
VDD
R (^) G
R (^) G
Vin
Cin
Cout
R (^) L
Vout
FIGURE 4.
The circuit shown in Fig 4 has the following parameters : VDD = 12V , RG1 = 16kΩ , RG2 = 12kΩ , RD = 100Ω , Vt = 3V and RL = 1kΩ. For the MOSFET , ID = 1mA when VGS = 3.5V.
(a) Find I (^) D , V (^) GS , VDS and prove that the MOSFET is in saturation. [ 8 marks ]
(b) What is the voltage gain? [ 4 marks ]
(c) If the circuit has a resistor of 50Ω added between the source and ground , calculate the new I (^) D value. [ 8 marks ]
