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Cork Institute of Technology
Bachelor of Engineering (Honours) in Electronic Engineering – Award
(Bachelor of Engineering in Electronic Engineering – Award)
(NFQ – Level 8)
Autumn 2005
Electronic Engineering
(Time: 3 Hours)
There are three sections (A, B and C) Answer any five questions with at least one from each section.
Please use separate answer books for each Section.
Each question carries equal marks (20) Maximum available mark is 100.
Examiners: Prof. C. Burkley Mr. J. Ryan Dr. J. Horan Dr. J. Barrett Dr. N. Barry
Section A
Q1. (a) Describe the operation of a switch capacitor resistor. What are the advantages of such a component over a passive resistor? Develop the equations for the equivalent resistance of this structure in terms of capacitance and switching clock frequency. [6 marks] (b) Describe the operation of a switch capacitor integrator and derive the sampled data transfer function from the charge transfer equations. [7 marks] (c) Describe the operation of a resistor string DAC with transmission gate Decoding. Comment on speed limitations in this architecture. [7 marks]
Q2. (a) Describe a circuit and the relevant equations commonly used to produce a voltage which is stable over process and temperature. How might this be modified to produce an output voltage referenced to ground, which is proportional to absolute temperature? [7 marks] (b) In the context of Sample and hold circuits. Explain the terms, Pedestal error, Isolation,Speed, Droop rate and Aperture jitter. In your answer discuss circuit features that influence these parameters. For a sample and hold made with a MOS switch, a capacitor and a unity gain buffer, derive an expression for the pedestal error in terms of the relevant switch parameters, the hold capacitor, the supply voltage and the input voltage to the sample and hold. [7 marks] (c) Explain the impact of Over-sampling on quantization noise in an AtoD converter. [6 marks]
Section B – Power Electronics
Q3. (a) By considering the flux in the inductor of a flyback converter (or otherwise) show that
using standard notation. [8 marks] (b) A 24W flyback converter has an input output voltage ratio of 12V/3V and operates at a duty cycle of 0.5. (i) What is the maximum voltage stress on the switch? [6 marks] (ii) If the ripple current in the inductor is 1A, what is the peak switch current? [6 marks]
Q4. (a) For a circuit taking a nonlinear current (with a sinusoidal applied voltage) what is the power factor and displacement factor? [5 marks]
(b) A full bridge rectifier circuit supplies a highly inductive load. Show that the power factor is 0.9. [10 marks]
(c) Consider the boost circuit below (Fig. Q4) fed from a full bridge rectifier. Devise a control strategy that will give a near unity input power factor for the circuit. [5 marks]
v(t)
gen.ac v^ o
Fig. Q
k
k N
N
Vo = Vs 1 1 − 2
Q7. (^) RF Power Amplifiers (a) From the tables and graphs from an RF power MOSFET datasheet in Figure Q7 on the next page, find: (i) The intermodulation distortion at 945MHz, IDQ=500mA, output power=20W, VDD=28V. [2 marks] (ii) The drain efficiency at an output power of 10W at 945MHz, IDQ=350mA, VDD=28V. [2 marks] (iii) The power gain in dB when the input power is 1W at 945MHz, IDQ=350mA, VDD=28V. [2 marks]
(b) What is intermodulation distortion and what causes it? [4 marks]
(c) A parallel LC resonant circuit is often placed between the output of an RF power amplifier and ground. To what frequency is the resonant circuit tuned and what function does it perform? [4 marks]
(d) The input impedance of an RF amplifier is 8-j2Ω and its output impedance is 6+j4Ω. Design input and output matching networks to match this amplifier to a 50 Ω source and 50 Ω load at 868MHz, blocking DC at input and output.
Q8. Oscillators (a) In Figure Q8 below, a resonant circuit for an oscillator is shown: (i) What type of components are C1 and C2? [2 marks] (ii) What are C1 and C2 used for in the circuit? [2 marks] (iii) What do we mean when we refer to the “sensitivity” of this circuit in Hz/V? [3 marks] (iv) What is CP used for in the circuit? [3 marks]
Figure Q
(b) Phase noise is a common problem in oscillators: (i) List two causes of phase noise. [2 marks] (ii) What effect does phase noise have on the output frequency spectrum of an oscillator? [2 marks] (iii) List two negative effects of oscillator phase noise in transmitters and receivers. [2 marks] (iv) What do we mean when we use “dBc/Hz” as the unit of measurement for phase noise? [4 marks]
