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Exception Processing Mechanism: RTL, Instruction Interpretation, and Extra Instructions, Slides of Computer Architecture and Organization

Himgiri Zee UniversityComputer Architecture and Organization

The exception processing mechanism using behavioral rtl, instruction interpretation, and additional instructions such as svi, ri, edi, and rfi. It covers saving and restoring interrupt information (ii) and interrupt program counter (ipc), enabling and disabling exceptions, and returning from interrupts.

Typology: Slides

2011/2012

Uploaded on 11/03/2012

dharmaraaj
dharmaraaj 🇮🇳

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1
SRC Exception Processing Mechanism
Interrupt Request
ireq:
Interrupt
Acknowldge
iack:
Disable
Interrupt
Flag IE:
Save PC
in IPC<31...0>
Load PC with
Exception Vector
Ivect<31…0>
Get interrupt
Info.
Isrc-info
<15…0>
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pf4
pf5
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1

SRC Exception Processing Mechanism

Interrupt Request ireq:

Interrupt Acknowldge iack:

Disable Interrupt Flag IE :

Save PC in IPC<31...0>

Load PC with Exception Vector Ivect<31…0>

Get interrupt Info. Isrc-info <15…0>

2

Behavioral RTL

for Exception Processing

Instruction_interpretation:=

(!Run&Strt: Run ← 1:

Run & !(ireq&IE):(IR ←M[PC],

PC ← PC + 4;

Instruction_execution),

Run&(ireq&IE): (IPC ← PC<31..0>,

II<15..0> ← Isrc_info<15..0>,

IE ← 0: PC ← Ivect<31..0>,

Iack ← 1; Iack ← 0) ,

Instruction_interpretation);

Meaning Start Normal Fetch

Interrupt, PC copied II is loaded with the info. PC loaded with new address

4

Step Concrete RTN

TO (^) (!(ireq&IE): (MA ← PC, C ← PC + 4);

(ireq&IE): (IPC ← PC,II← Isrc_info, IE ← 0,PC ← 22 α 0©Isrc_vect<7..0> © 00,iack ← 1;iack ← 0,End);

T1 MD ← M[MA],PC ← C;
T2 IR ← MD;

T3 Instruction_execution;

Structural RTL for Exception Processing

5

Combining the RTL for

reset and exception

Instruction interpretation:= Events

Run&!Rst&!(ireq&IE):(IR ← M[PC],

PC ← PC+4;

Normal Fetch

Run&Rst:( Rst ←0 , IE ← 0, PC ← 0 Soft Reset

!Run&Strt:(Run ←1, PC ← 0, R[0..31] ← 0; Hard Reset

Run&!Rst&(ireq&IE):(IPC ← PC<31..0>,

II<15..0> ← Isrc_info<15..0>,IE ← 0,

PC ← Ivect<31..0>,iack ← 1; iack ← 0;

Interrupt

7

Pipeline Stages

  • 5 pipeline stages are shown

1. Fetch instruction

2. Fetch operands

3. ALU operation

4. Memory access

5. Register write

  • 5 instructions are executing

1. ld r1, a ; memory access

2. st r2, b ; idle

3. add r4, r2, r3 ; ALU op

4. sub r6, r7, r5 ; idle

5. shr r1, r2, 4 ; write back

Fetch Inst.

Fetch Operand

ALU Operation

Memory Access

Register shr r1, r2, 4 Write

sub r6, r7, r

add r4, r2, r

st r2, b

ld r1, a

8

•Ifetch: Instruction Fetch

•Reg/Dec: Operand Fetch and Instruction Decode

•Exec: ALU operation

•Mem: Memory access stage

•Wr: Write the data back to the register file

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

lw^ Ifetch^ Reg/Dec^ Exec^ Mem^ Wr

Pipeline Stages: alternate notation

10

Branch Delay brzr r2, r add r6, r7, r8 ;This instruction is always executed st r6, addr1 ;Only done if r2 ≠ 0

Load Delay ld r2,addr add r5, r1, r2 ;This instruction gets “old”value of r shr r1,r1, sub r6, r8, r2 ;This instruction gets r2 value loaded from addr

Branch and Load Delay example

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