VHDL Packages and Libraries: Sharing and Reusing VHDL Code with Packages and TextIO, Study notes of Electrical and Electronics Engineering

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VHDL in Action

Packages and Libraries

Ch 3, pp. 96-

Martin 2003 (^2)

Last time

z Version of waveform updating

algorithm to handle reject

clauses

z Macro and micro time

z Delta delays: Ensure correct

ordering of zero time events

Martin 2003 (^3)

Covered in This Lesson

z Packages

z Libraries

z TextIO

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Motivation

z Why have subprograms?

• Readability
• Design re-use
• Sharing

z Packages and libraries are the

mechanism for design re-use and

sharing

Packages

z Observations:

• Including function and procedure

declarations within

ARCHITECTURE / PROCESS blocks

is awkward.

• Can't share between architectures

• Not very readable

• Not very maintainable

• Have to cut/paste subprogram into

every unit that uses it…

Packages (cont'd)

z Better approach:

• Group logically related sets of

functions and procedures into a

module that can be easily shared

among distinct designs and

people.

• Promote reuse

• Easier to maintain

• Package

Martin 2003 (^7)

Package Preview

z A Package contains two parts:

z Package declaration:

PACKAGE pname IS

< prototypes of package components>

END pname;

z Contains list of available package

components, functions, types,

procedures, etc.

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Package Preview (cont'd)

z Package Body

PACKAGE BODY pname IS

< Contains package component definitions>

END pname;

z A listing of the implementations

of package components

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Example Package(1 of 2)

PACKAGE sub_std_logic_1164 IS TYPE std_ulogic IS ( 'U', --uninitialized 'X', -- forcing unknown '0', -- forcing 0 '1', -- forcing 1 'Z', -- high impedance 'W', -- weak unknown 'L', -- weak low 'H', -- weak high '-' -- don't care ); Martin 2003 (^10)

Example Package(2 of 2)

TYPE std_ulogic_vector IS ARRAY (Natural RANGE <>) OF std_ulogic;

FUNCTION "AND" ( l, r : std_ulogic) RETURN std_ulogic; FUNCTION "AND" ( l, r : std_ulogic_vector) RETURN std_ulogic_vector; FUNCTION "AND" ( l : std_ulogic_vector, r : std_ulogic) RETURN std_ulogic_vector; COMPONENT dff PORT ( d, clk : IN std_ulogic; q : OUT std_ulogic); END COMPONENT; END sub_std_logic_1164;

Example Package Body

PACKAGE BODY sub_std_logic_1164 IS FUNCTION "AND" ( l, r : std_ulogic) RETURN std_ulogic IS VARIABLE tmp : std_ulogic; BEGIN tmp := ‘1’ WHEN l = ‘1’ AND r=‘1’ ELSE ‘0’ WHEN l=‘0’ OR r=‘0’ ELSE ‘X’; RETURN( tmp); END “AND”; o o

Example Package Body

FUNCTION "AND" ( l, r : std_ulogic_vector) RETURN std_ulogic_vector IS VARIABLE tmp : std_ulogic_vector; BEGIN ASSERT l’range = r’range; REPORT “Ranges must be equal for vector AND”; SEVERITY ERROR; FOR k in l’range LOOP tmp(k) := l(k) AND r(k); END LOOP; RETURN tmp; END “AND”;

Martin 2003 (^13)

Example Package Body

FUNCTION "AND" ( l: std_ulogic_vector; r: std_ulogic) RETURN std_ulogic_vector IS VARIABLE tmp : std_ulogic_vector; BEGIN FOR k in l’range LOOP tmp(k) := l(k) AND r; END LOOP; RETURN tmp; END “AND”;

END sub_std_logic_1164;

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Referencing Packages

z USE Clauses

• Placed before an entity declaration,

giving the entity and associated

architectures access to the package

contents

• Syntax:

USE library.package_name.component ;

USE work.sub_std_1164.dff, work.mypack.tff;

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Auto Package

z The package STANDARD is automatically

made visible to all entities.

z STANDARD defines:

• Bit
• Bit_Vector
• Boolean
• Integer
• Real
• Character
• String
• Time

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Libraries

z Design units are analyzed (compiled) and placed in libraries z Logical library names map to physical directories z Libraries STD and WORK are implicitly declared, i.e. don't have to have "LIBRARY WORK;" in file

Libraries

z When multiple design units are in the same file, visibility of libraries and packages must be established for each primary design unit (entity, package header, configuration) separately! z The use clause may selectively establish visibility, e.g., only the function rising_ edge() is visible within entity design-

Libraries--Doh!

z How about this:

library IEEE; entity test_libs is port (clk : in bit; data_out : out bit); end test_libs; architecture oh_no of test_libs is -- use ieee.std_logic_1164.all; signal s1 : std_logic; begin s1 <= '0'; end oh_no;

z If the entity makes the library visible, the

architecture can have the "use" statement

in the architecture.

Uncomment this line to compile correctly

Martin 2003 (^19)

Libraries--Doh!

z How about this:

entity test_libs2 is port (clk : in bit; data_out : out bit); end test_libs2;

architecture oh_no of test_libs2 is library ieee; use ieee.std_logic_1164.all; signal s1 : std_logic; begin s1 <= '0'; end oh_no;

z This won't compile--the library clause can't

appear in the declarative region of the

architecture.

• It will compile if the library clause is moved just before the architecture statement... Martin 2003 (^20)

USE Clauses

z To access all components of a

package:

USE work.sub_std_logic_1164. ALL;

z Note: packages can use material

defined in other packages:

USE work.basics.ALL;

PACKAGE more_detail IS

o

o

END more_details;

With this, a hierarchy of packages can be created.

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Visibility

z Reference to a

variable/signal/constant depends

upon the scope of the object and the

declaration region

z Reference to objects declared in a

higher scope can be made with.

(dot) notation:

B.X, WORK.SIG.X, Y.X

Martin 2003 (^22)

Visibility (1 of 3)

z Example from text:

PACKAGE sig IS SIGNAL x : Integer := 1; END sig;

USE work.sig; -- Package sig made visible ENTITY y IS SIGNAL x : Integer := 2; END y;

ARCHITECTURE z OF y IS SIGNAL z1, z2, z3, z4, z5 : Integer := 0; FUNCTION R RETURN INTEGER IS VARIABLE x : Integer := 3; BEGIN RETURN x; -- When R called, 3 returned END R;

Visibility (2 of 3)

BEGIN

B: BLOCK

SIGNAL x : Integer := 4;

SIGNAL z6: Integer := 0;

BEGIN

z6 <= x + y.x; -- z6 = 4 + 2

END BLOCK B;

o

o

o

Visibility (3 of 3)

PROCESS

VARIABLE x : Integer := 5; BEGIN z5 <= x; -- z5 = 5 WAIT; END PROCESS; z1 <= WORK.SIG.x; -- z1 = 1 z2 <= x; -- z2 = 2 z3 <= R; -- z3 = 3 z4 <= B.x; -- z4 = 4 END z;

Martin 2003 (^25)

Libraries

z Successfully analyzed models are

stored in a library

z A library may consist of several

models which

• may reference one another
• may be arranged in a hierarchical

fashion

z Two types of libraries:

• WORK: current analysis entered here
• RESOURCE: read-only reference libraries Martin 2003 (^26)

Libraries

z Libraries contain PRIMARY and

SECONDARY units:

z Primary units:

• Entities
• Package
• Configuration

z Secondary units:

• Architectures
• Package bodies

z Primary units must be analyzed before

corresponding secondary units.

z Both must be in the same library.

Martin 2003 (^27)

Library Names

z Libraries have LOGICAL and

PHYSICAL names:

z Logical name:

• Used by the VHDL model
• Portable, independent of the simulator

z Physical name:

• Used by the host operating system
• Dependent upon host platform

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Library Names

z The VHDL simulator must offer

some means of mapping Logical

names to Physical names:

• In LDV, mapping is in the CDS.lib file:

include $CDS_INST_DIR/tools/inca/files/cds.lib define work C:/tom/courses/4514f03/other_code/work

• Indirectly, the global CDS.lib file has:

DEFINE std ./STD DEFINE synopsys ./SYNOPSYS DEFINE ieee ./IEEE DEFINE ambit ./AMBIT

Making Libraries Visible

z To make a library visible, entry must exist

in mapping file

z In your VHDL code, visibility controlled by

LIBRARY command:

LIBRARY WORK; -- Automatic in all VHDL models LIBRARY IEEE;

z Access to library components is done with

the USE command:

USE IEEE.Std_Logic_1164.ALL; -- In the library IEEE, make the package -- STD_LOGIC_1164 visible to the -- following entity.

Creating Libraries

z Implementation dependent

z In LDV:

• Edit->Add->New Library
  • Give a logical name and a directory
• File->Set work library
  • Set this to the logical name
• Analyze code into the library
• Add library/use clauses to your other models
• Be sure to set work library back to your original work library

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Where the libraries roam

z In default install of LDV, IEEE

packages are in

• C:\Program Files\Cadence Design

Systems\LDV\tools\inca\files\IEEE.src

• std_logic_1164 package:

std_logic_1164.vhd

• It’s useful to look through the packages

for functions you can use…We’ll go

through them in class next week.

Martin 2003 (^32)

TextIO

z Files can be distinguished by the

type of information stored

z Package TEXTIO

• Declares: type line is access string;

type text is file of string ;

• Use STD.TextIO.all;

z VHDL 1987:

• file infile : text is in “inputdata. txt”;
• file outfile : text is out “outputdata. txt”;

Martin 2003 (^33)

Using TextIO: Example

procedure read_v1d(variable f:in text; v:out std_logic_vector) is variable buf : line; variable c : character ; begin -- do not forget appropriate library declarations readline (f , buf ); --read a line from the file. for i in v ’range loop read( buf , c ) ; --read a character from the line. case c is when ‘X’ => v (i) := ‘X’ ; when ‘U’ => v (i) := ‘U’ ; when ‘Z’ => v (i) := ‘Z’ ; when ‘0’ => v (i) := ‘0’ ; when ‘1’ => v (i) := ‘1’ ; when ‘-’ => v (i) := ‘-’ ; when ‘W’ => v (i) := ‘W’ ; when ‘L’ => v (i) := ‘L’ ; when ‘H’ => v (i) := ‘H’ ; when others => v (i) := ‘0 ’; end case; end loop; end; (From Yalamanchili) Martin 2003 (^34)

TextIO and testbenches

z Remember: Testbench instantiates

the system to be tested and a

stimulus driver

z Stimulus can be from:

• “on the fly” generation
• local constant arrays
• file I/O

z Can also save results to file for later

viewing…

Martin 2003 (^35)

Summary

z Packages and libraries

• Share your VHDL code with friends

and neighbors…

z TextIO

z Next time: Review for midterm