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Microcomputers
PIC24 Interrupts
1
Polled IO versus Interrupt Driven IO
• Polled Input/Output (IO) – processor continually
checks IO device to see if it is ready for data
transfertransfer
- Inefficient, processor wastes time checking for ready condition
- Either checks too often or not often enough
• Interrupt Driven IO – IO device interrupts
processor when it is ready for data transferp ocesso w e s e dy o d s e
- Processor can be doing other tasks while waiting for last data transfer to complete – very efficient.
- All IO in modern computers is interrupt driven.
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PIC24 C Interrupt Operation
The normal program flow (main) is referred to as the foreground code. The interrupt service routine (ISR) is referred to as the background code.
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
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Vector Table
This contains the starting address of the ISR for each interrupt source.
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
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Enabling an Interrupt
Each interrupt source generally has FLAG bit, PRIORITY bits, and an ENBLE bit.
The flag bit is set whenever the flag condition is true, which varies bby the interrupt. th i t t
The priority bits set the interrupt priority.
The enable bit must be ‘1’ for the ISR to be executed. (NOTE: the enable bit does not have to be a ‘1’ for the flag bit to be set!!!!!).
One of the things that must be done by the ISR is to clear the flag bit, or else the ISR will get stuck in an infinite loop.
By default, all priority bits and enable bits are ‘0’, so interrupt ISRs are disabled from execution.
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Traps vs. Interrupts
A Trap is a special type of interrupt, is non-maskable, has higher priority than normal interrupts. Traps are always enabled! Hard trap: CPU stops after instruction at which trap occursHard trap: CPU stops after instruction at which trap occurs
Soft trap: CPU continues executing instructions as trap is sampled and acknowledged
Trap Category Priority Flag(s) Oscillator Failure Hard 14 _OSCFAIL (oscillator fail, INTCON1<1>), _CF (clock fail, OSSCON<3>)CF (clock fail OSSCON<3>) Address Error Hard 13 _ADDRERR (address error, INTCON1<3>) Stack Error Soft 12 _STKERR (stack error, INTCON1<2>) Math Error Soft 11 _MATHERR (math error, INTCON1<4>) DMAC Error Soft 10 _DMACERR (DMA conflict write, INTCON1<5>) 8
Interrupt Latency
ISR Entry : Number of cycles from interrupt until 1 st^ instruction of ISR is executed.
ISR Exit : From RETFIE to program resumed.
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.^9
ISR Overhead
- Ientry : Number of instruction cycles for ISR entry (four on the PIC24 μC).
- Ibody : Number of instruction cycles for the ISR body (not iincluding l di retfietfi )).
- Iexit : Number of instruction cycles for ISR exit (three on the PIC24 μC).
- Fisr : Frequency (number of times per second) at which the ISR is triggered.
- Tisr : The ISR triggering period, which is 1/Fisr. For example, if an ISR is executed at 1 KHz, Tisr is 1 ms.
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Our _DefaultInterrupt ISR
UUsed for all d f ll interrupts when you do not provide an ISR. Our version saves the interrupt sourceinterrupt source, does a sofware reset, then interrupt source is printed. 13
Output from the _DefaultInterrupt ISR
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A User-provided ISR
These ISRs justThese ISRs just clear the _MATHERR interrupt flag and return. If the interrupt flag is not cleared, getg stuck in an infinite interrupt loop.
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Change Notification Interrupts
When enabled, triggers an interrupt when a change occurs on a pin. 16
Remappable Pins (cont.)
Output Name Function RP n R<4:0> Example Name Value Assignment Default Port Pin NULL 0 _RP n R = 0; UART1 TUART1 Transmit it U1TXU1TX 33 _RPRP R n R = 3; 3 UART1 Rdy. To Send U1RTS 4 _RP n R = 4; SPI1 Data Output SDO1 7 _RP n R = 7; SPI1 Clock Output SCK1OUT 8 _RP n R = 8; SPI1 Slave Sel. Out. SS1OUT 9 _RP n R = 9; Output Compare 1 OC1 18 _RP n R = 18; Output Compare 2 OC2 19 RP n R = 19;
Mapping outputs to RPx pins.
Output Compare 2 OC2 19 _RP n R 19;
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Remapping Macros
Contained in pic24_ports.h: CONFIG_U1RX_TO_RP(pin)
CONFIG_U1TX_TO_RP(pin)
etc.. Example Usage:
CONFIG_U1RX_TO_RP(10); //UART1 RX to RP
CONFIG_U1TX_TO_RP(11); //UART1 TX to RP
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INT2, INT1, INT0 Interrupts
These are input interrupt sources (INT x ) that can be configured to be rising edge triggered or falling-edge triggered by using an associated INTtriggered by using an associated INT xx EP bit (‘1’ is fallingEP bit ( 1 is falling edge, ‘0’ is rising edge’.
On the PIC24HJ32GP202, INT1 and INT2 must be brought out to remappable pins (RPx); INT0 is assigned a fixed pin location.
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//Interrupt Service Routine for INT void _ISRFAST _INT1Interrupt (void) { _INT1IF = 0; //clear the interrupt bit } /// Switch1 configuration, use RB inline void CONFIG_SW1() { CONFIG_RB13_AS_DIG_INPUT(); //use RB13 for switch input ENABLE_RB13_PULLUP(); //enable the pullup DELAY_US(1); // Wait for pull-up
Use INT1 to wake from Sleep mode
} int main (void) { configBasic(HELLO_MSG); /** Configure the switch ***********/ CONFIG_SW1(); CONFIG_INT1_TO_RP(13); //map INT1 to RP /** Configure INT1 interrupt */ _INT1IF = 0; //Clear the interrupt flag _INT1IP = 2; //Choose a priority _INT1EPINT1EP == 1;1; //negative//negative edgeedge triggerredtriggerred _INT1IE = 1; //enable INT1 interrupt while(1) { outString("Entering Sleep mode, press button to wake.\n"); //finish sending characters before sleeping WAIT_UNTIL_TRANSMIT_COMPLETE_UART1(); SLEEP(); //macro for asm("pwrsav #0") } } 22
T2IF Period
The T2IF flag is set at the following period ( Tt2if ): Tt2if = (PR2+1) x PRE x Tcy = (PR2+1) x PRE/Fcy
Observe that because Timer2 is a 16-bit timer, if PR2 is its maximum value of 0xFFFF (65535), and the prescaler is ‘1’, this is just: Tt2if = 65536 x 1/Fcy
We typically want to solve for Tt2if, given a PRE value:
PR2 = (Tt2if x Fcy /PRE ) − 1
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Example T2IF Periods
PR2/PRE Values for T (^) t2if = 15 ms, Fcy = 40 MHz PREPRE 1=1 PRE=8PRE 8 PRE=64PRE 64 PRE=256PRE 256
PR2 600000 75000 9375 2344
(invalid) (invalid)
The PR2 for PRE=1, PRE=8 are invalid because they are greater than 65535 (PR2 is a 16-bit register).
Configuring Timer2 to interrupt every T (^) t2if period is called a PERIODIC INTERRUPT.
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Timer2 Control Register
include\pic24_timer.h excerpts: /T2CON: TIMER2 CONTROL REGISTER/ #define T2_ON 0x #define T2 _OFF 0x #define T2_IDLE_STOP 0x #define T2_IDLE_CON 0x #define T2_GATE_ON 0x #define T2_GATE_OFF 0x #define T2_PS_1_1 0x #define T2_PS_1_8 0x #define T2_PS_1_64 0x #define T2_PS_1_256 0x #d fi T2 32BIT MODE ON 0 0008
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
#define T2_32BIT_MODE_ON 0x #define T2_32BIT_MODE_OFF 0x #define T2_SOURCE_EXT 0x #define T2_SOURCE_INT 0x
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Square Wave Generation
Timer2 configured to generate an interrupt every 15 ms. An output pin is toggled in the ISR, so square wave has period of 30 ms. Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
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Semaphores
Will use a ‘button press& release’ semaphore to implement this as one state
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
as one state
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Press&Release Semaphore
ISR is now a state machine!
Copyright Delmar Cengage Learning 2008. All Rights Reserved. From: Reese/Bruce/Jones, “Microcontrollers: From Assembly to C with the PIC24 Family”.
A semaphore is a flag set by an ISR when an IO event occurs. The main() code is generally responsible for clearing the flag. 32
main() code
Differences: Only one state used for each press and release.
Use the u8 pnrSW1_p semaphore to determine when press/release occurred. 33
Another Solution
PPut entire FSM into i FSM i the ISR instead of using a press&release semaphore.
Now use a doBlink semaphore to tell the main() code when to blink the LED.
Do not Blink in ISR! This delays exit from ISR. 34
