CS232 Fall 2006 Practice Final - MIPS, Pipelining, Caches, Virtual Memory, Parallelization, Exams of Computer Architecture and Organization

The cs232 fall 2006 practice final exam covering various topics including mips programming, pipelining, caches, virtual memory, and parallelization. The exam includes multiple-choice questions and programming problems. Students are required to translate a function into mips code, explain how to write a mips function with a function return value, analyze pipelining latency and throughput, determine the size of cache fields, and parallelize a code snippet.

Typology: Exams

Pre 2010

Uploaded on 03/11/2009

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CS232 Fall 2006 Practice Final December 10, 2006
1. MIPS:
Part A:
Translate the function func into MIPS. Assume that the function fhas already been translated. You must
observe all calling conventions.
int func(int a, int n) {
if(n == 0)
return a;
return f(func(a, n - 1));
}
Part B:
In a high-level language like C, it is possible for the return-type of a function to be a pointer to another
function. Explain how you would write a MIPS function whose return value is the function func from Part A.
Hint: Assume that the argument $a0 to your function is the address of a large chunk of memory to which
you can write. Your function should eventually return the value $a0.
2. Pipelining and ECC:
This problem asks you to apply the concept of pipelining to networks. A sender encodes the data as packets
(including parity bits for error detection) and transmits them over the network. The receiver inspects
the packets and sends an acknowledgement indicating whether or not an error was detected. Thus, the
transmission process for each packet can be broken into five stages:
Create (C): Create packet (data plus parity bit).
Send (S): Send the packet across the network.
Wait (W): Wait until an acknowledgement is received.
Receive (R): Receive acknowledgement packet.
Decode (D): Decode acknowledgement packet. If necessary, resend the original packet.
These five tasks are handled by independent hardware, and can therefore be pipelined. The latency of each
stage is given below:
Stage Latency (ms)
C 1.0
S 2.5
W 2.0
R 2.0
D 0.7
Part A:
(a) Compute the latency of each packet and maximum throughput (in packets per second) assuming a
5-stage pipeline.
(b) Any packet that gets corrupted must be re-sent. If every packet has a 10% probability of getting
corrupted, what is the expected time to send a packet?
Part B:
(a) Draw a pipeline diagram to indicate what the sender does when the acknowledgement indicates that
an error was detected.
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1. MIPS:

Part A: Translate the function func into MIPS. Assume that the function f has already been translated. You must observe all calling conventions.

int func(int a, int n) { if(n == 0) return a;

return f(func(a, n - 1)); }

Part B: In a high-level language like C, it is possible for the return-type of a function to be a pointer to another function. Explain how you would write a MIPS function whose return value is the function func from Part A. Hint: Assume that the argument $a0 to your function is the address of a large chunk of memory to which you can write. Your function should eventually return the value $a0.

  1. Pipelining and ECC:

This problem asks you to apply the concept of pipelining to networks. A sender encodes the data as packets (including parity bits for error detection) and transmits them over the network. The receiver inspects the packets and sends an acknowledgement indicating whether or not an error was detected. Thus, the transmission process for each packet can be broken into five stages:

Create (C): Create packet (data plus parity bit). Send (S): Send the packet across the network. Wait (W): Wait until an acknowledgement is received. Receive (R): Receive acknowledgement packet. Decode (D): Decode acknowledgement packet. If necessary, resend the original packet.

These five tasks are handled by independent hardware, and can therefore be pipelined. The latency of each stage is given below:

Stage Latency (ms) C 1. S 2. W 2. R 2. D 0.

Part A:

(a) Compute the latency of each packet and maximum throughput (in packets per second) assuming a 5-stage pipeline. (b) Any packet that gets corrupted must be re-sent. If every packet has a 10% probability of getting corrupted, what is the expected time to send a packet?

Part B:

(a) Draw a pipeline diagram to indicate what the sender does when the acknowledgement indicates that an error was detected.

(b) Based on your diagram above, describe what the receiver must do when it detects that an error in the packet. (c) Suppose each packet contains 8 bits ใ€ˆb 0 , b 1 ,... , b 7 ใ€‰. In the original scheme, there are 7 data bits ใ€ˆb 0 , b 1 ,... , b 6 ใ€‰ and one parity bit b 7 , where b 7 is the parity of the data bits. Consider a different scheme where each packet contains five data bits ใ€ˆb 0 , b 1 ,... , b 4 ใ€‰ and three parity bits: b 5 , b 6 and b 7. These bits are computed as follows:

b 7 = parity(ใ€ˆb 0 , b 1 ,... , b 4 ใ€‰) b 6 = parity(ใ€ˆb 0 , b 2 , b 4 ใ€‰) b 5 = parity(ใ€ˆb 1 , b 3 ใ€‰)

The original scheme could not detect two errors. Show that even with this new scheme, two errors cannot be detected.

  1. Caches:

Part A: A memory system has 32-bit byte addressable memory and a two-level cache with the following specifications:

L1 L Data size 32 KB 256 KB Block size 8 bytes 32 bytes Associativity direct mapped 4-way Hit time 1 cycle 19 cycles Miss rate 5% 2%

(a) Compute the size of the following fields: L1 L Block offset

Index size

Tag size

(b) If the AMAT of the L1 cache is 2 cycles, what is the miss penalty of the L2 cache?

Part B: Consider the following MIPS code that traverses an array of $a1 bytes 30,000 times:

$a0 is the base address of the array, $a1 is its length

li $t0, 0 # iterations of outer loop outer_loop: li $t1, 0 # iterations of inner loop move $t2, $a0 # copy base address into $t inner_loop: lb $t3, 0($t2) # temp = a0[t1] addi $t1, $t1, 1 # t1++ addi $t2, $t2, 1 bne $t1, $a1, inner_loop # repeat while t1 != a addi $t0, $t0, 1 # t0++ bne $t0, 30000, outer_loop