Digital Logic Design: Programmable Logic Devices and Their Notation - Prof. Peter D. Petro, Study notes of Electrical and Electronics Engineering

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ENEE244:

Digital Logic Design

Fall 2008

Instructor: Peter Petrov

Programmable Logic Devices

General structure of PLDs.

Buffer/inverter

PLD notation.

( a ) Unprogrammed and-gate. ( b ) Unprogrammed or-gate. ( c ) Programmed and-gate realizing the term ac****. ( d ) Programmed or-gate realizing the term a + b****. ( e ) Special notation for an and- gate having all its input fuses intact. ( f ) Special notation for an or-gate having all its input fuses intact. ( g ) And-gate with nonfusible inputs. ( h ) Or-gate with nonfusible inputs.

Types of PLDs

Device And-array Or-array PROM Fixed Programmable PLA Programmable Programmable PAL Programmable Fixed

PROM – Programmable ROM

PLA – Programmable Logic Array

PAL – Programmable Array Logic

A 2 n^ × m PROM.

( a ) Logic diagram.

( b ) Representation in PLD notation.

Using a PROM for logic design. (a) Truth table. ( b) PROM realization.

Example of combinational

logic design using a PLA.

( a) Maps showing the

multiple-output prime

implicants.

( b) Partial covering of the f 1 and f2 maps. ( c) Maps for the multiple-

output minimal sum.

( d) Realization using a 3 × 4 × 2 PLA.

General structure of a PLA having true and complemented output capability.

Karnaugh maps for the functions f1( x, y, z) = Σ m(1,2,3,7) and f2( x, y, z) = Σ m(0,1,2,6)

A simple four-input, three-output PAL device.

An example of using a PAL device to realize two Boolean

functions. ( a) Karnaugh maps. ( b) Realization.