Reconfigurable Computing - Computer Systems Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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Reconfigurable Computing

Reconfigurable Computing

Standard Definition : A reconfigurable computer is a device which computes by using post-fabrication spatial components of compute elements. [Dehon]

• FPGA implementation of a processor core to run a program is excluded - not spatial mapping of problem.
• ASIC implementations excluded – not postfabrication programmable.

The definition restricts RC to mapping to fine- grained devices (such as FPGAs).

Whereas General Purpose computers compute by making connections in time.

Spatial Computation

Example: grade = 0.2 × mt1 + 0.2 × **mt

• 0.2** × mt3 + 0.4 × project;

• A hardware resource (multiplier or adder) is allocated for each operator in the compute graph.
• The abstract computation graph becomes the implementation template.

Temporal Computation

• A hardware resource is time-multiplexed to implement the actions of the operators in the compute graph.
• Close to a sequential processor/software solution. Many inbetween cases exist.

Why is Custom Logic Faster Than

Software?

• Specialization
  • Instruction set may not provide the operations your program needs
  • Processors provide hardware that may not be useful in every program or in every cycle of a given program - Multipliers - Dividers
• Instruction Memory
  • Processors need lots of memory to hold the instructions that make up a program and to hold intermediate results.
• Bit Width Mismatches
  • In general, processors have a fixed bit width, and all computations are performed on that many bits - Multimedia vector instructions (MMX) a response to this

Microprocessor-based

Systems

• Generalized to perform many functions well.
• Operates on fixed data sizes.
• Inherently sequential.

Data Storage (Register File)

ALU

A B C

Dataflow

• Superscalar must find dataflow graph at run time
• RC constructs data flow graph at compile time
  • no logic control overhead
  • no window size limitations

Implementation Spectrum

• ASIC gives high performance at cost of inflexibility.
• Processor is very flexible but not tuned to the

application.

• Reconfigurable hardware is a nice compromise.

Microprocessor Reconfigurable Hardware

ASIC

Field-Programmable Gate Array

• Each logic element outputs one data bit.
• Interconnect programmable between elements.
• Interconnect tracks grouped into channels.

LE LE

LE LE

LE LE LE LE

LE LE

LE LE

Logic Element Tracks

Real World Physical Issues

• Modelling FPGA delay.
• Improving performance through buffering/segmentation.
• Technology dependent.
• The cost of reconfigurability.

S S

Wires have real cost

Translating a Design to an FPGA

• CAD to translate circuit from text description to physical implementation well understood.
• CAD to translate from C program to circuit not well understood.
• Very difficult for application designers to successfully write high- performance applications

C program

. . C = A+B .

Circuit

A B +^ C

Array

Need for design automation!

Reconfigurable Hardware

• Each logic element operates on four one-bit inputs.
• Output is one data bit.
• Can perform any boolean function of four inputs

2 = 64K functions!

Logic Element A B C D

Out

A B C D = out

Basic Logic Block Architecture