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Latch & Register Inference

Latch Inference

• In non-clocked processes, incompletely

specified if and case statements cause

synthesizers to infer latches for the

variables and signals being assigned.

Definition

• Basic Latch is a feedback connection of two NOR

gates or two NAND gates, which can store one bit

of information. It can be set to 1 using the S input

and reset to 0 using the R input.

• Gated Latch is a basic latch that includes input

gating and a control input signal. The latch retains

its existing state when the control input equals to

0. Its state may be changed when the control

signal is equal to 1.

Definition (cont..)

• Flip Flop: A flip flop is a storage element

based on the gated latch principle, which

can have its output state changed only on

the edge of the controlling clock signal.

• Two types of FF:

– Edge Triggered FF

– Level triggered FF

Waveform of D-ff

Register

• A flip-flop stores one bit of information.

When a set of n flip-flops is used to store n

bits of information, such as an n-bit number,

it is called Register.

• A common clock is used for each flip-flop

in a register.

Shift Left Register

• entity shifleft is
• Port ( newdata : in std_logic;
• datain : in std_logic_vector(3 downto 0);
• dataout : out std_logic_vector(3 downto 0);
• clk : in std_logic;
• reset : in std_logic);
• end shifleft;
• architecture Behavioral of shifleft is
• begin
• process (clk,reset,newdata)
• begin
• if (reset='1') then dataout <= "0000";
• elsif (clk'event and clk='0') then
• dataout <= datain(2 downto 0) & newdata;
• end if;
• end process;
• end Behavioral;

Waveform of Shift Left

Waveform of shift Right register

VHDL code for shift register

• entity shiftRegester is
• Port ( reset,clk,w : in std_logic; q : out std_logic_vector(3 downto 0));
• end shiftRegester;
• architecture Behavioral of shiftRegester is
• signal temp : std_logic_vector(3 downto 0);
• begin
• process(clk,reset)
• begin if (reset ='0') then q <= (others=>'0');
• elsif (clk'event and clk='1') then
• genbits: for i in 3 downto 1 loop
• temp(i) <= temp(i-1);
• end loop;
• temp(0) <= w; end if;
• q <= temp; end process;
• end Behavioral;

Serial-in Serial-out Shift Register

Serial in Parallel out

• architecture Behavioral of counterUP is
• signal count: std_logic_vector(3 downto 0);
• begin
• process(clk,reset,load,d)
• begin
• if (load='1') then
• count <= d; -- loadable counter
• elsif (reset='0') then
• count <= "0000";
• elsif (clk'event and clk='0') then
• if (count="1001") then -- decade counter
• count <= "0000" ;
• elsif (e ='1') then
• count <= count + 1;
• else count <= count - 1;
• end if;
• end if;
• end process; q <= count; end Behavioral;

Waveform of counter design