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Data Object - Computer Science - Lecture Slides, Slides of Computer Science

Amity University - BiharComputer Science

These are the Lecture Slides of Computer Science which includes Bit Adder, Code, Vector, Bcdcarryout, Architecture Behavioral, Component, Signal, Waveform, Logic etc. Key important points are: Data Object, Object Types, Represents, Interconnection, Instantiation Ports, Specific Values, Specific Type, Represent, Described, Dynamic Data

Typology: Slides

2012/2013

Uploaded on 03/23/2013

dhruv
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Data Object
Object Types
A VHDL object consists of one of the
following:
–Signal, Which represents interconnection wires
that connect component instantiation ports
together.
–Variable, Which is used for local storage of
temporary data, visible only inside a process.
–Constant, which names specific values.
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Data Object

Object Types

A VHDL object consists of one of the

following:

  • Signal, Which represents interconnection wires that connect component instantiation ports together.
  • Variable, Which is used for local storage of temporary data, visible only inside a process.
  • Constant, which names specific values.

Objects

  • Objects are used to represent & store the data in the system being described in VHDL.
  • Object contains a value of a specific type.
  • The name given to object is called identifier.
  • Each object has a type & class.
    • Class indicates how the object is used in the model & what can be done with the object.
    • Type indicates what type of data the object contains.
  • Each Signal name creates a new signal.
  • Separating the signal names from the signal

type is colon.

  • Signal type specifies the data type of the

information that the signal contains.

  • The signal can contain an initial value

specifier so that the signal value may

initialized.

  • Signals can be declared in entity declaration

sections, architecture declarations and

package declarations.

  • Signals in package declaration are also

referred to as global signals because they

can be shared among entities.

  • Each signal has a history of values I.e. holds

a list of values which include current value

of signal & set of possible future values

that are to appear on the signal.

  • Computed value is assigned to signal after

delay called ‘delta delay’.

architecture behave_signal of signal_example is

signal temp : std_logic;

begin

process (a) begin temp <= '1'; for i in 0 to 7 loop temp <= temp xor a(i); end loop; y <= temp; end process;

end behave_signal;

Waveform

  • Waveform show one input only
  • The keyword VARIABLE is followed by one or more variable names.
  • Each name creates a new variable.
  • The construct variable_type defines the data type of the variable, and an optional initial value can be specified.
  • Variable can be declared in the process declaration and subprogram declaration sections only.
  • Variable are inherently more efficient because assignments happen immediately, while signals must be scheduled to occur.
  • Variables take less memory, while signals need more information to allow for scheduling and signal attributes.
  • Using a Signal would have required a WAIT statement to synchronize the signal assignment to the same execution iteration as the usage.

architecture behave_variable of variable_example is

begin

process (a) variable temp: std_logic; begin temp := '0'; for i in 0 to 7 loop temp := temp xor a(i); end loop; y <= temp; end process;

end behave_variable;

Constants

  • Constant objects are names assigned to

specific values of a type.

  • Constants give the designer the ability to have

a better-documented model, and a model that

is easy to update.

  • Constant declaration :

Constant constant_name : type_name [:value];