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Main points of this exam paper are: Resolution, Provide Units, Expect, Silicon Dioxide Layer, Metal Layer, Better or Worse, Faster or Slower
Typology: Exams
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C. Nguyen March 18, 2010
INSTRUCTIONS
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C. Nguyen March 18, 2010
Problem 1.
Please provide short written answers to the questions that follow.
(a) Would you expect the resolution of lithography over a metal layer to be better or worse than over a silicon dioxide layer? Why?
(b) Would you expect oxidation to be faster or slower over <111> silicon when compared with <100> silicon? Why?
(c) You’ve just done a standard photoresist spin & bake, lithography, and etch step using a per- fectly anisotropic RIE. However, the sidewalls of the etched film are not straight. What is most likely causing this? What can you do to fix this in your next fabrication run?
Total 29 points
C. Nguy
Problem
T photoresi etch is 10 and that t the struct and (c) cross-sec wafer sur
en
m 2. The cross-se ist pattern on 00% anisotro the etch rate ture to the le 11 minutes ction. Also, f rfaces were b
Total ction of a n top is show opic; that the e of silicon ( eft of the do of etching. for each cas before any e
l 33 points
March 18
polysilicon- wn. The patt e selectivity and polysilic tted line afte Be sure to se use dotted etching.
-oxide-silico tern will be of silicon (a con) is 0.1 μ er (a) 2 minu o specify re d lines to ind
on substrate etched via R and polysilic μm/min. Car utes of etchi elevant angle dicate where
sandwich RIE. You can con):SiO 2 :ph refully draw ing; (b) 5 mi es and dim e the origina
Mo
structure w n assume tha hotoresist = 2 cross-sectio inutes of etc ensions for al photoresis
ore work sp
with a at the 2:1:1; ons of ching; each st and
ace next page.
C. Nguyen March 18, 2010
Problem 2. (continued)
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C. Nguyen March 18, 2010
Problem 3.
The structure shown below has gone through the following process steps: i) Start with a bare 〈 100 〉 silicon wafer. ii) Grow 300 nm of oxide. iii) Deposit 100 nm of Si 3 N 4. iv) Lithography: Mask 1. v) Etch 100 nm of Si 3 N 4 and m nm of SiO 2. vi) Remove PR. vii) Wet oxidation @ 1000o^ C for t minutes. Determine t and m.
Total 20 points
SiO 2
Si 3 N (^4)
0.3 (^) μm
0.05 (^) μm
0.2 μm Silicon
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C. Nguyen March 18, 2010
Problem 3. (continued)
C. Nguyen March 18, 2010
Problem 4. (continued) xvii) Oxidize a bit (10nm) and anneal at 1050o^ C to activate dopants and drive-in diffusion. xviii) LPCVD PSG: target = 1μm. xix) Reflow PSG (& a little bit of diffusion) at 950o^ C. xx) Lithography: Mask III (contact hole). xxi) Dry/wet etch SiO 2 down to n+ S/D regions. xxii) Sputter Al: target = 500nm. xxiii) Lithography: Mask IV (metal). xxiv) Dry etch Al to clear the field areas. Here’s where things start to differ from standard LOCOS-isolated NMOS. xxv) Lithography: Mask V (release). xxvi) Dip in hydrofluoric acid for 10 minutes. xxvii) Remove PR.
Instructions: Draw the cross-section along the A-A′ axis at the end of this process, giving important vertical and lateral dimensions.
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C. Nguyen March 18, 2010
Extra Page.