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C. Nguyen May 10, 2010
INSTRUCTIONS
Read all of the instructions and all of the questions before beginning the exam.
There are 5 problems on this Final Exam, totaling 143 points. The tentative credit for each part is given to help you allocate your time accordingly. You have a total of 3 hours to finish this exam. Be careful not to spend all your time on any one part.
This is a closed book exam, except you can have two two-sided 8.5″×11″ sheet of notes and a calculator.
Unless otherwise noted on a particular problem, you must show your work (in the space pro- vided plus the backs of the pages, if needed) for all problems to receive full credit; simply providing answers will result in only partial or no credit, even if the answers are correct. If you require extra space beyond what is provided, be sure to turn in any material that is required to support your solutions. Note that there are extra pages at the end of this exam. Do not use any attached pages until you have exhausted the pages contained in this exam.
Turn in the entire exam, including this cover sheet.
Put your name on every page of this exam, as well as on any additional material that you submit.
Be sure to provide units where necessary.
Signature : ___________________________________________
Problem 1: / 38 points
Problem 2: / 25 points
Problem 3: / 20 points
Problem 4: / 25 points
Problem 5: / 35 points
Total: / 143 points
C. Nguyen May 10, 2010
Problem 1.
Please provide short written answers to the questions that follow.
(a) Which technology was the first in volume production, NMOS or PMOS, and why?
(b) Are substrate doping levels higher or lower in modern (i.e., today’s) CMOS versus 1990’s CMOS? Why?
(c) A silicon wafer is uniformly doped with boron (to 2x10^15 cm-3) and phosphorus (to 1x10^15 cm-3) so that it is net p-type. This wafer is then thermally oxidized to grow about 1 μm of SiO 2. The oxide is then stripped and a measurement is made to determine the doping type of the wafer surface. Surprisingly it is found to be n-type. Explain why the surface was converted from p- to n-type.
Total 38 points
C. Nguyen May 10, 2010
Problem 1. (continued)
(g) In LOCOS oxidation, patterned films of nitride on oxide are used to block oxidation over ac- tive area regions. Unfortunately, LOCOS also introduces “bird’s beaks” that encroach into the active regions, and this limits how small an MOS device can be made. Can we suppress the bird’s beak in LOCOS by dispensing with the oxide film and instead depositing nitride directly over silicon? What would be the problem with this approach? Explain.
(h) Suppose you plan to use a stepper projection lithography tool to pattern polysilicon over oxide. The tool uses an exposure wavelength of 200 nm and has a numerical aperture of 0.5. What is the minimum theoretical feature size that this tool can resolve? What is the maximum height of topography over the wafer surface that this tool can handle while maintaining this resolution?
C. Nguyen May 10, 2010
Problem 2.
The cross-section for a standard, LOCOS-isolated, nwell CMOS technology (similar to the pwell process described in lecture) is shown below.
(a) Label all layers in the process, including n+ and p+ diffusions. Also, delineate thermal oxides from LPCVD oxides. Then use wires (i.e., lines) and batteries to implement an inverter in this technology, hooking up relevant portions to V DD and ground, and clearly indicating inputs and outputs.
(b) Draw on the figure the cross-section of a guard ring at a location that provides the most ef- fective protection against latch-up. Indicate the dopant type used and the bias voltage to which this ring is attached. Explain why this location is better than any other. Draw parasitic tran- sistors and current direction arrows to aid in your explanation
Total 2 5 points
C. Nguyen May 10, 2010
Problem 3. (continued)
C. Nguyen May 10, 2010
Problem 4.
The drain currents for four NMOSFETs on the same die with the same Wdrawn ’s (=50m), but with different Ldrawn ’s, were measured for two different VGS ’s, with drain voltages set at 50mV, and sources and bulks tied to ground. The resulting data are summarized as follows:
Ldrawn [m] 2 4 6 8 Id ( VGS = 3V) [A] 16 6.9 4.5 3. Id ( VGS = 6V) [A] 28 12.7^ 8.2^ 6.
For this problem, assume that the effective channel width Weff = Wdrawn , the threshold voltage Vt = 0.7V, and the gate oxide thickness Xox = 20nm, for all devices. Also assume that for a device with no external series resistance Rext , the drain current Id in the linear region (i.e., with small VDS ) is given approximately by
Use the data and the graph paper below to determine the following parameters:
(a) the external resistance in series with the channel, Rext
(b) L = Ldrawn – Leff , where Leff is the effective channel length considering all sources of deviation
(c) the low field mobility, o; and
(d) of the devices.
Total 2 5 points
C. Nguyen May 10, 2010
Problem 4. (continued)
C. Nguyen May 10, 2010
Problem 5.
The simplified CMOS process flow used to fabricate an NMOS transistor is as follows: i) CMOS twin-well processing steps to form nwell’s and pwell’s, both with doping Nsu b=??? cm-3, and standard LOCOS to define active areas. ii) Sacrificial oxide growth: Target = 30 nm, 900oC, 20 min. dry O 2. iii) Threshold implant: B11, E = 10 keV, DI =???cm-2. iv) Strip sacrificial oxide. v) Gate oxidation: 900oC, 12 min. dry O 2 + 20 min. N 2 anneal. Target = 10 nm. vi) Polysilicon gate deposition: 650oC, 1 hr. 35 min. Target = 250 nm. vii) Gate definition. viii) Re-oxidation: 900oC, 14 min. dry O 2 + 10 min. N 2 anneal. Target = 20 nm SiO 2 on poly. ix) n+ S/D implant and anneal: 925oC, 20 min. in N 2. x) p+ S/D implant. xi) PSG deposition: 450oC. Target = 300 nm. xii) PSG densification: 925oC, 20 min. wet O 2. xiii) Contact hole mask. xiv) Metal deposition, masking, and patterning. xv) Low temperature sintering.
After fabricating an NMOS device using the above process flow, measurements are taken on the device to yield a plot of threshold voltage V t versus the square root of the inversion surface po- tential magnitude | s | plus V SB as shown below.
s + VSB [V1/2]
V
[V] t
Total 35 points
C. Nguyen May 10, 2010
Problem 5. (continued)
More work space next page.
C. Nguyen May 10, 2010
Problem 5. (continued)
C. Nguyen May 10, 2010
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