Computer Engineering Exam 3, Spring 2001 - Memory Systems, Instruction Formats, Datapath, Exams of Computer Science

The spring 2001 exam three for the computer engineering course, ece 2030 c. The exam covers various topics including memory systems, instruction formats, datapath elements, microcode reverse engineering, and a saturating counter state machine. Students are required to solve problems related to these topics, some of which include calculating the number of chips and banks required for different memory systems, determining the instruction format values, analyzing datapath elements, and reverse engineering microcode. The exam consists of five problems and five pages.

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2012/2013

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ECE 2030 C Computer Engineering Spring 2001
5 problems, 5 pages Exam Three 19 April 2001
1
Problem 1 (3 parts, 24 points) Memory Systems
Imagine using a 4 Mbit DRAM organized as 1 million addresses of 4-bit words to build three memory
systems. The following three parts consider memory systems built using this chip.
Part A (8 points) Consider a 16 Mbit memory system organized as 4 million addresses of 4-bit words.
number of chips needed in one bank 4bits/bank / 4bits/chip = 1 chip/bank
number of banks for memory system 4M/system / 1M/bank = 4 banks/system
memory decoder required (n to m)2 to 4
number of DRAM chips required 1 chip/bank * 4 banks/sys = 4 chips
Part B (8 points) Consider a 16 Mbit memory system organized as 1 million addresses of 16-bit words.
number of chips needed in one bank 16bits/bank / 4bits/chip = 4 chips/bank
number of banks for memory system 1M/system / 1M/bank = 1 banks/system
memory decoder required (n to m)not required
number of DRAM chips required 4 chip/bank * 1 bank/sys = 4 chips
Part C (8 points) Consider an 256 Mbit memory system organized as 32 million addresses of 8-bit
words.
number of chips needed in one bank 8bits/bank / 4bits/chip = 2 chips/bank
number of banks for memory system 32M/system / 1M/bank = 32 banks/system
memory decoder required (n to m)5 to 32
number of DRAM chips required 2 chip/bank * 32 banks/sys = 64 chips
Problem 2 (1 part, 10 points) Instruction Formats
Suppose a datapath has three operand busses (two source, one destination), 100 instruction types, and
64 registers where each register is 32 bits wide. Immediate operands can be in the range of ±4K.
Determine the following values for the resulting instruction format. For the last two questions, assume the
same operand number and types used in the MIPS format.
bits needed to specify an opcode 7
bits needed to specify a register operand 6
bits needed to specify an immediate operand 13
bits needed to specify an R-format instruction 7 + 6 + 6 + 6 = 25
bits needed to specify an I-format instruction 7 + 6 + 6 + 13 = 32
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5 problems, 5 pages Exam Three 19 April 2001

Problem 1 (3 parts, 24 points) Memory Systems Imagine using a 4 Mbit DRAM organized as 1 million addresses of 4-bit words to build three memory systems. The following three parts consider memory systems built using this chip. Part A (8 points) Consider a 16 Mbit memory system organized as 4 million addresses of 4-bit words. number of chips needed in one bank 4bits/bank / 4bits/chip = 1 chip/bank number of banks for memory system 4M/system / 1M/bank = 4 banks/system memory decoder required ( n to m ) 2 to 4 number of DRAM chips required 1 chip/bank * 4 banks/sys = 4 chips

Part B (8 points) Consider a 16 Mbit memory system organized as 1 million addresses of 16-bit words. number of chips needed in one bank 16bits/bank / 4bits/chip = 4 chips/bank number of banks for memory system 1M/system / 1M/bank = 1 banks/system memory decoder required ( n to m ) not required number of DRAM chips required 4 chip/bank * 1 bank/sys = 4 chips

Part C (8 points) Consider an 256 Mbit memory system organized as 32 million addresses of 8-bit words. number of chips needed in one bank 8bits/bank / 4bits/chip = 2 chips/bank number of banks for memory system 32M/system / 1M/bank = 32 banks/system memory decoder required ( n to m ) 5 to 32 number of DRAM chips required 2 chip/bank * 32 banks/sys = 64 chips

Problem 2 (1 part, 10 points) Instruction Formats Suppose a datapath has three operand busses (two source, one destination), 100 instruction types, and 64 registers where each register is 32 bits wide. Immediate operands can be in the range of ±4K. Determine the following values for the resulting instruction format. For the last two questions, assume the same operand number and types used in the MIPS format. bits needed to specify an opcode 7 bits needed to specify a register operand 6 bits needed to specify an immediate operand 13 bits needed to specify an R-format instruction 7 + 6 + 6 + 6 = 25 bits needed to specify an I-format instruction 7 + 6 + 6 + 13 = 32

5 problems, 5 pages Exam Three 19 April 2001 Problem 3 (2 parts, 25 points) Datapath Elements Part A (12 points) For the eight bit word below, determine the result of a performing the shift operation specified. Each shift type should assume the same input value. Assume the shifter word width is eight bits.

Input Value: 1 1 0 0 1 0 1

Shift type Count Result

logical +2 0 0 1 1 0 0 1 0

logical -2 0 0 1 0 1 0 0 0

arithmetic +2 1 1 1 1 0 0 1 0

arithmetic -2 0 0 1 0 1 0 0 0

rotate +2 1 0 1 1 0 0 1 0

rotate -2 0 0 1 0 1 0 1 1

Part B (13 points) Assuming X controls S0 and Y controls S1, determine the logical function produced by the logical unit multiplexer, given the input values (LF 3 -LF 0 ) listed below. Y X out 0 0 LF 0 0 1 LF 1 1 0 LF 2 1 1 LF 3 LF 3 LF 2 LF 1 LF 0 Logical Function

0 0 0 1 X^ + Y

0 0 1 1 Y

0 1 1 1 X^ ⋅ Y

5 problems, 5 pages Exam Three 19 April 2001

Problem 5 (5 parts, 16 points) Saturating Counter State Machine Consider a state machine implementation of a two-bit saturating up/down counter. The state machine has one input: up / down , and two outputs: Out 0 and Out 1 , which also indicate the next state. When up / down is high, the counter counts up (00, 01, 10, 11, 11, 11,…). When up / down is low, the counter counts down (11, 10, 01, 00, 00, …). It is a saturating counter, which means the counter doesn’t “roll-over”, when it hit the maximum or minimum count. When 00 is reached, the counter stays in 00 in response to a low up / down signal. (Similarly, when the maximum count state (11) is reached, the counter stays there when up / down is high.)

Part A (8 points) Complete the state diagram below by adding all required transition arcs with input annotations. Output annotations are not required since they correspond to the new state.

U

U

U

U D

D

D D

Part B (8 points) Now complete the state table from the state diagram. up / down S 1 S 0 Out 1 Out 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1