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The solutions to problem 1, 2, 3 and 4 of exam three for the computer engineering course ece 2030, fall 2003. The problems cover various topics such as instruction formats, memory systems, datapath elements, and microcode reverse engineering.
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4 problems, 3 pages Exam Three Solution 19 November 2003
Problem 1 (3 part, 12 points) Instruction Formats
An instruction format has the following field lengths for R-type and I-type instructions. Answer the following questions:
opcode RD RS1 RS 12 bits 9 bits 9 bits 9 bits opcode RD RS1 immediate value 12 bits 9 bits 9 bits 28 bits
Part A (4 points) How many registers are there? (^512)
Part B (4 points) How many instruction types are there? (^) 4K
Part C (4 points) What is the range of immediate values? (^) -127M to +128M
Problem 2 (3 parts, 32 points) Memory Systems
Part A (12 points) Consider a 4 Gbit DRAM chip organized as 512 million addresses of 8 bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal.
number of columns (^2 32) = 216 = 64 K
column decoder required ( n to m ) 16 to 64K type of mux required ( n to m ) 64K / 8 = 8K to 1
number of muxes required 8 number of address lines in column number log 2 (64K) = 16 number of address lines in column offset log 2 (8K) = 13
Part B (10 points) Consider a 256 Mbyte memory system with 64 million addresses of 4 byte words using 16 Mbit DRAM chips organized as 4 million addresses by 4 bit words.
word address lines for memory system log 2 (64M) = 26
chips needed in one bank 4*8 / 4 = 8 banks for memory system 64M / 4M = 16
memory decoder required ( n to m ) 4 to 16 DRAM chips required 8 * 16 = 128
4 problems, 3 pages Exam Three Solution 19 November 2003
Part C (10 points) Design an 8M x 8 bit memory system with four 4M x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a decoder if necessary.
4M x 4
D D D D
ADDR
CS
4M x 4
D D D D
ADDR
CS
4M x 4
D D D D
ADDR
CS
ADDR
23
MSEL
D D D D
4M x 4
D D D D
ADDR
CS
D D D D
1 to 2 decoder
S
EN
O
O
22
A
A21:
22
22
22
22
Problem 3 (2 parts, 21 points) Datapath Elements
Part A (9 points) Suppose the following inputs (in hexadecimal) are applied to the 32-bit barrel shifter used in the datapath. Determine the output (in hexadecimal). Shift Type Shift Amount Input Value Output Value logical 10 87654321 (+16 bits) 00008765
arithmetic 14 87654321 (+20 bits) FFFFF
rotate 30 87654321 (-16 bits) 43218765
Part B (12 points) For each logical function (LF) specification below (in hexadecimal), determine the bitwise logical function computed by the logical unit. The mapping table is listed below left.
X Y Out LF logical function LF logical function
0 0 LF 0 9 X ⊕ Y^1 X + Y
1 0 LF 1 7 X ⋅ Y F^1
0 1 LF 2 5 X^4 X ⋅ Y
1 1 LF 3 C Y^ D^ X^ + Y