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Chapter 7 – Analysis and Design of Sequential Circuits
Chapter Overview Up to this point we have considered two types of circuits: the basic set of combinational circuits and the simple sequential circuits called flip-flops. This chapter will discuss more complex sequential circuits fabricated from these basic elements. We have seen the four basic types of flip-flops. We now use them in design problems.
Chapter Assumptions Again, the presumption is that the student is familiar with Boolean logic and basic combinational circuitry. Although many students will have had a previous introduction to flip-flops, no familiarity with the devices is assumed.
Introduction to Sequential Circuits We have spent some time considering combinational circuits. Combinational circuits are the basis of all digital devices, yet they do not suffice for any but the simplest devices. The one significant weakness of combinational circuits is that they do not have memory.
The inadequacy of pure combinational logic can be illustrated by considering a simple device – the soft drink machines in every campus building. Currently, the price of a soft drink is $0.90. A machine controlled by only combinational logic would have 2 options:
- If a dollar bill or dollar coin is inserted, return a drink and $0.10 in change.
- If a smaller coin is inserted, return the coin and indicate that it is not big enough.
Clearly, the behavior of the “combinational logic soft drink machine” is not acceptable. One expects the machine to have a memory to store the amount of money to be applied to the next purchase. What we want is for the soft drink machine to be controlled by sequential logic, specifically by a FSM (Finite State Machine). In this example, the SDM (Soft Drink Machine) is initialized to a state called 0 – there has been no money deposited for a drink. When one places a quarter into the machine, it enters a state called 25 – there has been $0.25 deposited. In state 25, the machine waits for a money deposit in excess of $0.65 total before it will dispense a drink and possibly change. If the SDM accepts nickels, dimes, quarters, and dollar coins, it is easy to show that the number of states is finite: 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, and 100 – a total of 21 states.
Finite state machines are studied in most courses in computer architecture. We note in passing that all stored program computers are theoretically finite state machines, although it is not profitable to view them as such. Consider a computer with 64 KB of memory – an extremely small value. This corresponds to 512K bits =
524, 288 bits. The memory alone of such a computer is a FSM with 2^524288 » 2.5·10^157826 states – that is a 25 followed by 157,285 zeroes. We might as well call that an infinite number.
For this course it suffices to note that we must have digital devices with memory and to investigate the most common ways of providing such memory. In electrical engineering terms, memory is a feedback mechanism, in which the output of a combinational circuit is delayed for some amount of time and then fed back as input to the circuit.
The concept of feedback is helpful to the small number of us with background in an engineering discipline, but most of us will prefer to think of memory as “bit boxes”
- storage containers that hold one bit of binary information. These bit boxes, called “flip-flops”, were discussed in the previous chapter.
Before discussing memory devices, let’s review the difference between combinational circuits and sequential circuits.
Combinational Circuits Sequential Circuits No Memory Memory
No flip-flops, Flip-flops may be used only combinational gates Combinational gates may be used
No feedback Feedback is allowed
Output for a given set of The order of input change Inputs is independent of is quite important and may order in which these inputs produce significant differences were changed, after the in the output. output stabilizes.
The following figure shows a way to consider sequential circuits.
Figure: Sequential Logic Includes Combinational Logic and Memory
Sequential circuits can be characterized into two broad classes – synchronous and asynchronous. As a general rule, asynchronous circuits are faster, but much harder to design. We shall focus totally on synchronous circuits.
By Q(T) we denote the state of a sequential circuit at time T – this is basically its memory. We watch the state of the circuit change from Q(T) to Q(T + 1) as the clock ticks. The constraint on synchronous circuits is that the state of the circuit changes after the input, thus we have a typical sequence as follows:
- At time T, we have input (denoted by X) and state Q(T).
Figure: State Diagram for a 11011 Sequence Detector
At this stage of the presentation, we focus not on the details of generating the state diagram, but just use it as an example of a generic state diagram. What do we note about this one?
- In terms of discrete mathematics, it is a directed graph with loops. Thus, it is not a simple graph. In simple graphs, arcs do not connect any vertex with itself.
- The arcs each have direction and a label of the form X/Z. What we see here is the FSM reacting to input by moving between states and producing output. In the X/Z labeling scheme, X is the binary input (0 or 1) and Z is the binary output.
- There is output associated with the transitions. Not all FSM have output associated with the transitions between states. This one does.
- This and all typical FSM represents a synchronous machine; transitions between states and production of output (if any) takes place at a fixed phase of the clock, depending on the flip-flops used to implement the circuit.
Not all finite state machines have such complex state diagrams.
The figure at left is the state diagram for a modulo- up-counter. It just counts 0, 1, 2, 3 and repeats, continually counting up (modulo 4). There is no input (other than the clock, which we almost never mention) and no output directly associated with the transitions. For this type of FSM, the output is associated with the states and not with the transitions.
Figure: State Diagram for a Modulo-4 Up-Counter
Many mathematical models of FSM focus on the state diagram. For most of our work, it is more convenient to work with the state table of the FSM, a tabular representation of the state diagram. Translation between the state diagram and state table is automatic. The state table presents the data in terms of present state Q(t) and next state Q(t+1) using the labeling that most naturally fits the problem. Here are the state tables for the two FSM above. Note that eh state table contains exactly the same information as the state diagram.
Present State Next State / Output X = 0 X = 1 A A / 0 B / 0 B A / 0 C / 0 C D / 0 C / 0 D A / 0 E / 0 E A / 0 C / 1 Figure: State Table for 11011 Sequence Detector, Showing Output
Present State Next State 0 1 1 2 2 3 3 0 Figure: State Table for a Modulo-Four Up-Counter
One notes immediately that the second state table is simpler than the first; this is expected it represents a simpler state diagram. Specifically there is no input, so there is only one column for the next state. In
general, for K inputs there are 2 K^ next state columns in the table.
Another tool in the design and analysis of sequential circuits is the transition table. It contains the same information as the state table, except that all labels have been replaced by binary numbers. There are many creative ways to assign binary numbers to state labels, here we just do the obvious. For the sequence detector, let A = 000, B = 001, C = 010, D = 011, and E = 100 (as there are five states). The following is the sequence detector transition table.
Present State Next State / Output X = 0 X = 1 A = 000 000 / 0 001 / 0 B = 001 000 / 0 010 / 0 C = 010 011 / 0 010 / 0 D = 011 000 / 0 100 / 0 E = 100 000 / 0 010 / 1 Figure: Transition/Output Table for the 11011 Sequence Detector
Circuit for Analysis We first study the analysis of digital circuits, then we study their design. There are a number of steps in the analysis of a circuit. Where to begin depends on what one has. When given a circuit diagram, the following steps are used to begin the analysis.
- Determine the inputs and outputs of the circuit. Assign variables to represent these.
- Determine the inputs and outputs of the flip-flops.
- Construct the Next State and Output Tables.
- Construct the State Diagram.
- If possible, identify the circuit. There are no good rules for this step.
Consider the following circuit. We want to discover what it does.
Figure: Circuit to Be Analyzed
Step 1: Identify and Label the Inputs, Outputs, and Internal States
We use the following variables in the analysis of this circuit with a single flip-flop. X denotes the input, Y denotes the output of the flip-flop (Y’ also), and Z the output of the circuit. If we had more than one flip- flop, we would label the flip-flop with a number beginning at 0 and use that as a subscript, so flip-flop 0 would have output Y 0 , etc.
Step 2: Determine the Inputs and Outputs of the Flip-flops
The next step is to determine the equations for Z, the output, and D, the input to the flip-flop. By inspection, we determine the following for the equations: Z = X Å Y D = X + Y
Step 3: Construct the Next State and Output Tables. We begin this state by recalling the characteristic table of each flip-flop that is used in the design. Here we have only one flip-flip, a D with a very simple characteristic table that is better represented as an equation: Q(t+1) = D – the next state is what you put in now.
Noting that Q(t) = Y (the state of a flip-flop is also its output) we construct the following Next-State diagram for the flip-flop, based on the characteristic table of a D flip-flop and the equation we derived for the D input: D = X + Y.
One simple caution here is that the input to a flip-flop is a function of the present state only, having nothing to do with the next state (as we have no crystal balls). Thus Y = Q(t). Here is the present state (PS) / next state (NS) diagram for the circuit.
X Q(t) = Y D = X + Y Q(t+1) 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1
The output table is similarly constructed, using the equation Z = X Å Y = Z = X Å Q(t). Again, note that the output is not a function of the next state.
X Q(t) Z 0 0 0 0 1 1 1 0 1 1 1 0
These two tables are combined to form the transition / output table.
X Q(t) = Y D = X + Y Q(t+1) / Z 0 0 0 0 / 0 0 1 1 1 / 1 1 0 1 1 / 1 1 1 1 1 / 0
At this point, we should produce a state table in the standard format. This involves assigning labels to each of the two states, currently identified only as Q(t) = 0 and Q(t) = 1. For lack of anything more imaginative, we label the states 0 and 1.
Present State Next State/Output X = 0 X = 1 0 0 / 0 1 / 1 1 1 / 1 1 / 0
Figure: State Table for Circuit to be Analyzed
Design of Sequential Circuits Having seen how to analyze digital circuits, we now investigate how to design digital circuits. We assume that we are given a complete and unambiguous description of the circuit to be designed as a starting point. At this level, most design problems focus on one of two topics: modulo-N counters and sequence detectors.
Here is an overview of the design procedure for a sequential circuit.
- Derive the state diagram and state table for the circuit.
- Count the number of states in the state diagram (call it N) and calculate the number of flip-flops needed (call it P) by solving the equation 2 P-1^ < N £ 2P^. This is best solved by guessing the value of P.
- Assign a unique P-bit binary number (state vector) to each state. Often, the first state = 0, the next state = 1, etc.
- Derive the state transition table and the output table.
- Separate the state transition table into P tables, one for each flip-flop. WARNING: Things can get messy here; neatness counts.
- Decide on the types of flip-flops to use. When in doubt, use all JK’s.
- Derive the input table for each flip-flop using the excitation tables for the type.
- Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops.
- Summarize the equations by writing them in one place.
- Draw the circuit diagram. Most homework assignments will not go this far, as the circuit diagrams are hard to draw neatly.
Design Problem: A Modulo-4 Counter As our first design problem, let’s consider a modulo-four counter. When the direction is not specified, we usually intend to build a modulo-four up-counter: 0, 1, 2, 3, 0, 1, 2, 3, etc. We solve these design problems by using the step-wise procedure listed above.
Step 1: Derive the state diagram and state table for the circuit.
Here is the state diagram. Note that it is quite simple and involves no input.
Figure: The State Diagram for a Modulo-4 Up Counter
The state table is simply a rearrangement of the state diagram into a tabular form.
Present State Next State 0 1 1 2 2 3 3 0
Step 2: Count the number of states in the state diagram (call it N) and calculate the
number of flip-flops needed (call it P) by solving the equation 2P-1^ < N £ 2P^.
The number of states on a modulo-N counter is simply N; these are labeled 0 through (N – 1). Specifically, a modulo-4 counter has four states: labeled 0, 1, 2, and 3.
We solve the equation 2P-1^ < 4 £ 2P^ by noting that 2^1 = 2 and 2 2 = 4, so we have determined that 2^1 < 4 £ 2 2 , hence P = 2. We shall see later that there are valid solutions with more than two flip-flops, but there are none with fewer.
Step 3 Assign a unique P-bit binary number (state vector) to each state. Often, the first state = 0, the next state = 1, etc.
Some sequential circuits suggest an innovative numbering system, but modulo-N counters never do. We go with the obvious labeling, generated by assigning each decimal number its two-bit binary equivalent as an unsigned integer in the range from 0 to 3.
State 2-bit Vector 0 0 0 1 0 1 2 1 0 3 1 1
Step 4 Derive the state transition table and the output table.
There is no output table for any modulo-N counter, as the output associated with this type of table is the output on a transition, as is seen in a sequence detector. The transition table is a direct translation of the state table, using the assignments from the previous step.
Present State Next State 0 00 01 1 01 10 2 10 11 3 11 00
Here is the table for Y
PS NS Input Y 1 Y 0 Y 0 J 0 K 0 0 0 1 1 d 0 1 0 d 1 1 0 1 1 d 1 1 0 d 1
Again, Y 1 is included in the table for future use only. It plays no part in determining the values of J 0 and K 0.
Step 8 Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops.
At this point, we try to derive an expression that matches each column. Formal methods can be used, but generally are more trouble than they are worth. Here is this author’s set of rules to match an expression to a given column.
- If a column does not have a 0 in it, match it to the constant value 1. If a column does not have a 1 in it, match it to the constant value 0.
- If the column has both 0’s and 1’s in it, try to match it to a single variable, which must be part of the present state. Only the 0’s and 1’s in a column must match the suggested function.
- If every 0 and 1 in the column is a mismatch, match to the complement of a function.
- If all the above fails, try for simple combinations of the present state.
Let’s look at the input table for Y 1.
PS NS Input Y 1 Y 0 Y 1 J 1 K 1 0 0 0 0 d 0 1 1 1 d 1 0 1 d 0 1 1 0 d 1
Note that the column for J 1 has a 0 and a 1 in it as does the column for K 1. Each column has two “don’t cares” in it, but we ignore these. Because each column has both a 0 and a 1 in it, neither is a match for a constant function. We now try to match J 1.
J 1 does not match Y 1 , because Y 1 is 0 in the same row (0 1) as J 1 is 1. J 1 matches Y 0. In row 0 0, both Y 0 and J 1 are 1. In row 0 1, both Y 0 and J 1 are 1. In rows 1 0 and 1 1, J 1 is a “don’t care”, so we do not need to match it.
Similar logic shows that K 1 matches Y 0 also.
So now we have the following matches for J 1 and K 1.
PS NS Input Y 1 Y 0 Y 1 J 1 K 1 0 0 0 0 d 0 1 1 1 d 1 0 1 d 0 1 1 0 d 1 J 1 = Y 0 K 1 = Y 0
We now examine Y (^0)
PS NS Input Y 1 Y 0 Y 0 J 0 K 0 0 0 1 1 d 0 1 0 d 1 1 0 1 1 d 1 1 0 d 1
Note that there are no 0’s in either the J 0 or K 0 column. The simplest (and best) match is
J 0 = 1 and K 0 = 1.
Step 9 Summarize the equations by writing them in one place. Here they are. J 1 = Y 0 K 1 = Y 0 J 0 = 1 K 0 = 1
This is a counter, so there is no Z output.
Step 10 Draw the circuit diagram.
Note that the above design is simplified by the fact that the outputs Y 1 ’ and Y 0 ’ are available directly from
the flip-flops and do not need to be synthesized using NOT gates.
One can achieve a simpler design at the cost of additional flip-flops. The following design is called a one- hot design, in that it uses a shift register in which exactly one flip-flop at a time is storing a 1. This design also works as a modulo-4 counter and skips the decoder delays.
When the counter is initialized, we set Y 0 = 1, and Y 1 = Y 2 = Y 3 = 0. As the clock ticks, the single 1 is shifted by the shift register, so that the discrete signals become high in sequence.
Another Design Problem: The Modulo-4 Up-Down Counter For the next design, we introduce a problem that uses input. This is a modulo-4 up-down counter. The input X is used to control the direction of counting. If X = 0, the device counts up: 0, 1, 2, 3, 0, 1, 2, 3, etc. If X = 1, the device counts down: 0, 3, 2, 1, 0, 3, 2, 1, etc.
Step 1: Derive the state diagram and state table for the circuit.
The state diagram for the modulo-4 up-down counter is shown at right. Notice that the X input is used to determine the counting direction. Again, this type of circuit does not have any output associated with the transitions; the output just reflects which of the four states the machine finds itself in at the moment.
We now produce the sate table by translating the state diagram. As an aside, some students might prefer to begin the design process with the state table and omit the state diagram. That is certainly acceptable practice; whatever works should be used.
Here, the state table depends on X – the input used to specify the counting direction.
Present State Next State X = 0 X = 1 0 1 3 1 2 0 2 3 1 3 0 2
Step 2: Count the number of states in the state diagram (call it N) and calculate the
number of flip-flops needed (call it P) by solving the equation 2P-1^ < N £ 2P^.
The number of states on a modulo-N counter is simply N; these are labeled 0 through (N – 1). Specifically, a modulo-4 counter has four states: labeled 0, 1, 2, and 3.
We solve the equation 2P-1^ < 4 £ 2P^ by noting that 2^1 = 2 and 2 2 = 4, so we have determined that 2^1 < 4 £ 2 2 , hence P = 2. We shall see later that there are valid solutions with more than two flip-flops, but there are none with fewer.
Step 3 Assign a unique P-bit binary number (state vector) to each state. Often, the first state = 0, the next state = 1, etc.
Some sequential circuits suggest an innovative numbering system, but modulo-N counters never do. We go with the obvious labeling, generated by assigning each decimal number its two-bit binary equivalent as an unsigned integer in the range from 0 to 3.
State 2-bit Vector 0 0 0 1 0 1 2 1 0 3 1 1
Step 4 Derive the state transition table and the output table.
There is no output table for any modulo-N counter, as the output associated with this type of table is the output on a transition, as is seen in a sequence detector. The transition table is a direct translation of the state table, using the assignments from the previous step.
Step 7 Derive the input table for each flip-flop using the excitation tables for the type.
Here is the input table for flip-flop 1. Note that the arrangement of the table has been altered to reflect the fact that we now have a binary input.
X = 0 X = 1
Y 1 Y 0 Y 1 J 1 K 1 Y 1 J 1 K 1
0 0 0 0 d 1 1 d 0 1 1 1 d 0 0 d 1 0 1 d 0 0 d 1 1 1 0 d 1 1 d 0
Here is the input table for flip-flop 0.
X = 0 X = 1
Y 1 Y 0 Y 0 J 0 K 0 Y 1 J 0 K 0
0 0 1 1 d 1 1 d 0 1 0 d 1 0 d 1 1 0 1 1 d 1 1 d 1 1 0 d 1 0 d 1
Step 8 Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops.
At this point, we try to derive an expression that matches each column. Formal methods can be used, but generally are more trouble than they are worth. Here is this author’s set of rules to match an expression to a given column.
- If a column does not have a 0 in it, match it to the constant value 1. If a column does not have a 1 in it, match it to the constant value 0.
- If the column has both 0’s and 1’s in it, try to match it to a single variable, which must be part of the present state. Only the 0’s and 1’s in a column must match the suggested function.
- If every 0 and 1 in the column is a mismatch, match to the complement of a function.
- If all the above fails, try for simple combinations of the present state.
The reader will note that there are two columns for each variable for which an equation is desired; one column for X = 0 and one column for X = 1. For example, consider the table for flip-flop 0, just above. If we work on a column-by column basis, we shall arrive at four equations. One for J 0 when X = 0,
one for K 0 when X = 0, one for J 0 when X = 1, and one for K 0 when X = 1.
However, we need a single equation for J 0 and a single equation for K 0.
The Combine Rule There are many ways to produce the single equations for J 0 and K 0 , including algebraic simplification and
Karnaugh Maps. The method preferred by this author for producing a single equation for an entity such as J (^0) or K 0 is as follows.
- Use the “least complexity” matching rule as described above for each column of the expression. Thus, for J 0 , we shall have two expressions, one for X = 0 and one for X = 1.
- Use this author’s “combine rule” to produce a single expression.
The rule for combining expressions derived separately for X = 0 and X = 1 is X’·(expression for X= 0) + X·(expression for X = 1).
The origin of the combination rule is the following observation. Consider the Boolean expression F = X’·A
- X·B, where A and B are any Boolean expressions. When X = 0, this becomes F = 1·A + 0·B = A, and when X = 1, this becomes F = 0·A + 1·B = B.
We then see that F = X’·A + X·B if and only if F = A when X = 0 and F = B when X = 1. This simple observation is the source of the combination rule. It will always produce a correct result and usually produce the simplest result.
There are quite a few simplifications of the combine rule, all of which should be noted.
- A = B. Then F = X’·A + X·A = A
- A = 0. Then F = X’·0 + X·B = X·B B = 0 Then F = X’·A + X·0 = X’·A
- A = 1 Then F = X’·1 + X·B = X’ + B (by the Absorption Theorem) B = 1 Then F = X’·A + X·1 = A + X (also by the Absorption Theorem)
The last two statements seem somewhat surprising, so we prove them. a) X’ + X·B = X’ + B If X = 0, then X’ + X·B = 1 + 0·B = X’ + B = 1 + B = 1 If X = 1, then X’ + X·B = 0 + 1·B = B X’ + B = 0 + B = B
b) X’·A + X = A + X If X = 0, then X’·A + X = 1·A + 0 = A A + X = A + 0 = A If X = 1, then X’·A + X = 0·A + 1 = 1 A + X = A + 1 = 1
So we get to work with the combine rule.
