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Analysis and Design of Sequential Circuits, Slides of Digital Logic Design and Programming

Ankit Institute of Technology and Science Digital Logic Design and Programming

An in-depth exploration of various types of sequential circuits, including synchronous and asynchronous circuits, sr latches, flip-flops, and their analysis using state tables and diagrams. It covers topics such as j-k flip-flops, mealy and moore models, and state reduction.

Typology: Slides

2011/2012

Uploaded on 07/24/2012

pariya 🇮🇳

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Sequential Circuits

Combinational circuits

Output = f (present inputs)

Sequential circuits

Output = f (present inputs and past inputs)

Circuit remembers past history

Must contain memory

inputs k n outputs

present state next state

combinational

circuit

memory

state

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Sequential Circuits ^ Combinational circuits^

Output = f (present inputs)

^ Sequential circuits

^ Output = f (present inputs and past inputs) ^ Circuit remembers past history ^ Must contain memory

inputs

k^

n outputs

present state

next state

combinational

circuit memory

m^

m

state

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Synchronous Sequential Circuits A synchronizing, periodic signal, Clock, facilitatesthe transition from present state to next state^ ^

Memory is provided by flip-flops

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SR (Set Reset) Latches NAND Latch SR = 00 is avoided^ ^

Outputs are not complementary

Input transition from 00

Æ

11 may cause circuit to: (i) fall

into either state, or become meta-stable

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SR Latch with control Input C = 0^ ^

Latch retains its state

C = 1

Allows propagation of SR inputs

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Flip-flop Latch Is level sensitive to the control signal^

Multiple data transition may cause problem while C =

Flip-flop is edge triggered

Flip-flop samples the data on Clock transition

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Edge Triggered Flip-flop Efficient implementation^

Multiple data transitions do not affect the output

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J-K Flip-flop

Qn+

= JQ

’ + K’Qn

= Dn

JK

Qn

Qn+

J^

K^

Qn^

Qn+

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Asynchronous Inputs Ability to Reset (or Set)irrespective of Clockstate^

Often needed incomputation

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State Table

Present State

Input

Next State

Output

A^00001111

B^

A^

B^

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State Table, State Diagram Present State

Next State

Output

x =

x = y 0 1 1 1

AB^00011011

AB^

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State Table^ Present State

Input

Next State

Flip-flop Inputs

A^

JA^

KA^

JB

B^

A^

B^

KB

A(t+1) = JA’ + K’AB(t+1) = JB’ + K’B

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State Diagram

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Analysis with Toggle Flip-flop

PresentState

Input

Next State

Output

B^

y 0 1 1 0 0 1 1 0

A^0000111

B^

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Mealy and Moore Models (Machine) ^

Most general model of a sequential circuit has inputs,outputs, and internal states

Two different models – (i) Mealy model, (ii) Moore Model

^

Difference is how output is generated Mealy Model

Output is a function of present state & input

Moore Model

Output is only a function of present state

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Analysis and Design of Sequential Circuits, Slides of Digital Logic Design and Programming

Related documents

Partial preview of the text

Download Analysis and Design of Sequential Circuits and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Sequential Circuits ^ Combinational circuits^

Output = f (present inputs)

^ Sequential circuits

inputs

k^

n outputs

present state

next state

combinational

circuit memory

m^

m

state

Synchronous Sequential Circuits  A synchronizing, periodic signal, Clock, facilitatesthe transition from present state to next state^ ^

Memory is provided by flip-flops

SR (Set Reset) Latches  NAND Latch  SR = 00 is avoided^ ^

Outputs are not complementary

Input transition from 00

Æ

11 may cause circuit to: (i) fall

into either state, or become meta-stable

SR Latch with control Input  C = 0^ ^

Latch retains its state

C = 1

Allows propagation of SR inputs

Flip-flop  Latch Is level sensitive to the control signal^

Multiple data transition may cause problem while C =

Flip-flop is edge triggered

Flip-flop samples the data on Clock transition

Edge Triggered Flip-flop  Efficient implementation^

Multiple data transitions do not affect the output

J-K Flip-flop

Qn+

= JQ

’ + K’Qn

= Dn

JK

Qn

Qn+

J^

K^

Qn^

Qn+

Asynchronous Inputs  Ability to Reset (or Set)irrespective of Clockstate^

Often needed incomputation

State Table

A^00001111

B^

A^

B^

State Table, State Diagram Present State

AB^00011011

AB^

AB^

State Table^ Present State

A^

JA^

KA^

JB

B^

A^

B^

KB

A(t+1) = JA’ + K’AB(t+1) = JB’ + K’B

State Diagram

Analysis with Toggle Flip-flop

B^

A^0000111

B^

Mealy and Moore Models (Machine) ^

Most general model of a sequential circuit has inputs,outputs, and internal states

Two different models – (i) Mealy model, (ii) Moore Model

^

Difference is how output is generated Mealy Model

Moore Model

Sequential Circuits ^ Combinational circuits^

^ Sequential circuits

Synchronous Sequential Circuits A synchronizing, periodic signal, Clock, facilitatesthe transition from present state to next state^ ^

SR (Set Reset) Latches NAND Latch SR = 00 is avoided^ ^

SR Latch with control Input C = 0^ ^

Flip-flop Latch Is level sensitive to the control signal^

Edge Triggered Flip-flop Efficient implementation^

Asynchronous Inputs Ability to Reset (or Set)irrespective of Clockstate^

Mealy and Moore Models (Machine) ^

^