Copyright © 2007 Elsevier <1>
Chapter 3 : Sequential Logic Design
Digital Logic Design
James E. Stine, Jr.
Portions of slides taken from Digital Design and Computer Architecture
D. M. Harris and S. L. Harris, Elsevier, 2007
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Sequential Logic Design: FSMs, Latches, and Flip-Flops, Papers of Electrical and Electronics Engineering
A chapter from 'digital logic design' by james e. Stine, jr. It covers the topics of finite state machines (fsms), latches and flip-flops, and their encoding and decoding. Examples, diagrams, and tables to illustrate the concepts.
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Chapter 3 : Sequential Logic Design
Digital Logic Design
James E. Stine, Jr.
Portions of slides taken from Digital Design and Computer Architecture
D. M. Harris and S. L. Harris, Elsevier, 2007
Chapter 3 :: Topics
- Latches and Flip-Flops
- Synchronous Logic Design
- Finite State Machines
Moore vs. Mealy FSM
- Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last four
digits it has crawled over are 1101. Design Moore and Mealy
FSMs of the snail’s brain.
State Transition Diagrams reset Moore FSM S 0 0
S 1
S 2
S 3
S 4
reset S 0 S 1 S 2 S 3 0 / 0
Mealy FSM Mealy FSM: arcs indicate input/output
Moore FSM Output Table
S
2
S
1
S Y
0
Current State Output
Y = S
2
Mealy FSM State Transition and Output Table
Current State Input Next State Output 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 S' 1 0 1 0 0 1 0 S' 0 1 1 0 0 0 0 S 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 S 0 A Y
S3 11
S2 10
S1 01
S0 00
State Encoding
Mealy FSM Schematic S' 1 S' 0 CLK Reset S 1 S 0 A Y S 0 S 1
Moore and Mealy Timing Diagram Mealy Machine Moore Machine
CLK
Reset A S Y S Y Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 ?? S 0 S 1 S 2 S 3 S 4 S 2 S 3 S 4 S 0
S 2
?? S 0 S 1 S 2 S 2 S 3 S 1 S 2 S 3 S 1 S 0
Introduction
- Outputs of sequential logic depend on current and prior input values.
- Sequential logic thus has memory.
- Some definitions:
- State: contains all the information about a circuit
necessary to explain its future behavior
- Latches and flip-flops: state elements that store one bit
of state
- Synchronous sequential circuits: combinational logic
followed by a bank of flip-flops
Sequential Circuits
• give sequence to events
• have memory (short-term)
• use feedback from output to input to store
information
Bistable Circuit
- Fundamental building block of other state elements
- Two outputs: Q , Q
- No inputs Q Q Q Q I 1 I 2 I 2 I 1
Bistable Circuit Analysis Q Q I 1 I 2 0 1 1 0
- Consider the two possible cases:
- Q = 0: then Q = 1 and Q = 0 (consistent)
- Q = 1: then Q = 0 and Q = 1 (consistent)
- Bistable circuit stores 1 bit of state in the state variable, Q (or
Q )
- But there are no inputs to control the state Q Q I 1 I 2 1 0 0 1
SR Latch Analysis
- Consider the four possible cases:
- S = 1, R = 0
- S = 0, R = 1
- S = 0, R = 0
- S = 1, R = 1
SR Latch Analysis
- S = 1, R = 0: then Q = 1 and Q = 0
- S = 0, R = 1: then Q = 0 and Q = 1 R S Q Q N 1 N 2 0 1 1 0 0 0 R S Q Q N 1 N 2 1 0 0 1 0 1