Sequential Logic Implementation - Components and Techniques for Digital Systems - Lecture Slides, Slides of Computer Science

These are the Lecture Slides of Components and Techniques for Digital Systems which includes Digital Hardware, Sound Design Methodologies, Modern Specification Methods, Basic Units of Computation, Physical Implementations, Switching Networks, Relay Networks etc. Key important points are: Sequential Logic, Sequential Circuits, Timing Methodologies, Asynchronous Inputs, Basic Registers, Circuits with Feedback, Static Memory Cell, Cross-Coupled Nor Gates, Timing Behavior

Typology: Slides

2012/2013

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Sequential Logic Implementation
Sequential Circuits
Primitive sequential elements
Combinational logic
Models for representing sequential circuits
Finite-state machines (Moore and Mealy)
Representation of memory (states)
Changes in state (transitions)
Basic sequential circuits
Shift registers
Counters
Design procedure
State diagrams
State transition table
Next state functions
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Sequential Logic Implementation

• Sequential Circuits

– Primitive sequential elements

– Combinational logic

• Models for representing sequential circuits

– Finite-state machines (Moore and Mealy)

– Representation of memory (states)

– Changes in state (transitions)

• Basic sequential circuits

– Shift registers

– Counters

• Design procedure

– State diagrams

– State transition table

– Next state functions

Abstraction of State Elements

• Divide circuit into combinational logic and state

• Localize feedback loops and make it easy to break

cycles

• Implementation of storage elements leads to

various forms of sequential logicCombinational

Logic

Storage Elements

Outputs

State Inputs State Outputs

Inputs

Finite State Machine Representations

  • States: determined by possible values in sequential

storage elements

  • Transitions: change of state
  • Clock: controls when state can change by controlling

storage elements

  • Sequential Logic
    • Sequences through a series of states
    • Based on sequence of values on input signals
    • Clock period defines elements of sequence

In = 0

In = 1

In = 1 In = 0

Example Finite State Machine Diagram

  • Combination lock from first lecture

reset

S

closed

closed mux=C1 equal & new

not equal & new

not equal & new

not equal & new

not new not new not new

S1 S2 OPEN

ERR

closed mux=C2 equal & new

closed mux=C3 equal & new

open

Counters are Simple Finite State

Machines

  • Counters
    • Proceed thru well-defined state sequence in response

to enable

  • Many types of counters: binary, BCD, Gray-code
    • 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110,

111, 000, ...

  • 3-bit down-counter: 111, 110, 101, 100, 011, 010,

001, 000, 111, ...

3-bit up-counter

How Do We Turn a State Diagram into

Logic?

  • Counter
    • Three flip-flops to hold state
    • Logic to compute next state
    • Clock signal controls when flip-flop memory can

change

  • Wait long enough for combinational logic to compute

new value

  • Don't wait too long as that is low performance

D Q D Q D Q

OUT1 OUT2 OUT

CLK

FSM Design Procedure: State Diagram

to Encoded State Transition Table

  • Tabular form of state diagram
  • Like a truth-table (specify output for all input

combinations)

  • Encoding of states: easy for counters – just use

value 010

100

110

001 011

000

111 101

3-bit up-counter

current state next state 0 000 001 1 1 001 010 2 2 010 011 3 3 011 100 4 4 100 101 5 5 101 110 6 6 110 111 7 7 111 000 0

Implementation

• D flip-flop for each state bit

• Combinational logic based on encoding

C3 C2 C1 N3 N2 N

N1 := C1'

N2 := C1C2' + C1'C

:= C1 xor C N3 := C1C2C3' + C1'C3 + C2'C := C1C2C3' + (C1' + C2')C := (C1C2) xor C

notation to show function represent input to D-FF

0 0

0 1

1 1

C1^0

C

N3 C

0 1

1 0

1 0

C1^0

C

N2 C

1 1

0 0

1 1

C1^0

C

N1 C

Another Example

• Shift Register

– Input determines next state

In C1 C2 C3 N1 N2 N 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1

N1 := In N2 := C N3 := C

100 110

111

011

000 010 101

001

0

1

1 1 1 1

1

1

0

0

0

0 0

1

0 0

IN^ D^ Q^ D^ Q^ D^ Q

OUT1 OUT2 OUT

CLK

More Complex Counter Example

• Complex Counter

– Repeats five states in sequence

– Not a binary number representation

• Step 1: Derive the state transition diagram

– Count sequence: 000, 010, 011, 101, 110

• Step 2: Derive the state transition table from

the state transition diagram

Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 – – – 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 – – – 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 – – – note the don't care conditions that arise from the unused state codes

Self-Starting Counters (cont’d)

• Re-deriving state transition table from don't

care assignment

0 0

1 1

0 0

A^1

B

C+ C

1 1

1 0

0 1

A^0

B

B+ C

0 1

0 1

0 0

A^0

B

A+ C

Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0

Self-Starting Counters

• Start-up States

– At power-up, counter may be in an unused or

invalid state

– Designer must guarantee it (eventually) enters a

valid state

• Self-starting Solution

– Design counter so that invalid states eventually

transition to a valid state

– May limit exploitation of don't cares

implementation on previous slide

State Machine Model (cont’d)

• States: S1, S2, ..., Sk

• Inputs: I1, I2, ..., Im

• Outputs: O1, O2, ..., On

• Transition function: Fs(Si, Ij)

• Output function: Fo(Si) or Fo(Si, Ij)

Inputs

Outputs

Next State

Current State

output logic

next state logic

Clock

Next State

State

0 1 2 3 4 5

Example: Ant Brain (Ward, MIT)

• Sensors: L and R antennae, 1 if in

touching wall

• Actuators: F - forward step, TL/TR - turn

left/right slightly

• Goal: find way out of maze

• Strategy: keep the wall on the right