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These are the Lecture Slides of Components and Techniques for Digital Systems which includes Digital Hardware, Sound Design Methodologies, Modern Specification Methods, Basic Units of Computation, Physical Implementations, Switching Networks, Relay Networks etc. Key important points are: Sequential Logic, Sequential Circuits, Timing Methodologies, Asynchronous Inputs, Basic Registers, Circuits with Feedback, Static Memory Cell, Cross-Coupled Nor Gates, Timing Behavior
Typology: Slides
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Finite State Machine Representations
storage elements
storage elements
Example Finite State Machine Diagram
reset
S
closed
closed mux=C1 equal & new
not equal & new
not equal & new
not equal & new
not new not new not new
S1 S2 OPEN
ERR
closed mux=C2 equal & new
closed mux=C3 equal & new
open
Counters are Simple Finite State
Machines
to enable
111, 000, ...
001, 000, 111, ...
3-bit up-counter
How Do We Turn a State Diagram into
Logic?
change
new value
FSM Design Procedure: State Diagram
to Encoded State Transition Table
combinations)
value 010
100
110
001 011
000
111 101
3-bit up-counter
current state next state 0 000 001 1 1 001 010 2 2 010 011 3 3 011 100 4 4 100 101 5 5 101 110 6 6 110 111 7 7 111 000 0
:= C1 xor C N3 := C1C2C3' + C1'C3 + C2'C := C1C2C3' + (C1' + C2')C := (C1C2) xor C
notation to show function represent input to D-FF
0 0
0 1
1 1
0 1
1 0
1 0
1 1
0 0
1 1
In C1 C2 C3 N1 N2 N 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1
N1 := In N2 := C N3 := C
100 110
111
011
000 010 101
001
0
1
1 1 1 1
1
1
0
0
0
0 0
1
0 0
Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 – – – 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 – – – 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 – – – note the don't care conditions that arise from the unused state codes
0 0
1 1
0 0
1 1
1 0
0 1
0 1
0 1
0 0
Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0
implementation on previous slide
Inputs
Outputs
Next State
Current State
output logic
next state logic
Clock
Next State
State
0 1 2 3 4 5