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Sequential Logic Examples
• Finite State Machine Concept
– FSMs are the decision making logic of digital designs
– Partitioning designs into datapath and control
elements
– When inputs are sampled and outputs asserted
• Basic Design Approach: 4-step Design Process
• Implementation Examples and Case Studies
– Finite-string pattern recognizer
– Complex counter
– Traffic light controller
– Door combination lock
General FSM Design Procedure
• (1) Determine inputs and outputs
• (2) Determine possible states of machine
– – State minimization
• (3) Encode states and outputs into a binary code
– – State assignment or state encoding
– – Output encoding
– – Possibly input encoding (if under our control)
• (4) Realize logic to implement functions for states and
outputs
– – Combinational logic implementation and optimization
– – Choices in steps 2 and 3 have large effect on resulting
logic
Finite String Pattern Recognizer
(Step 2)
- Step 2: Draw State Diagram
- For the strings that must be recognized, i.e., 010
and 100
S
[0]
S
[0]
S
[1]
S
[0]
0 or 1
S
[0]
S
[0]
S
[0]
reset
Finite String Pattern Recognizer (Step
2, cont’d)
- Exit conditions from state S3: have recognized
…
- If next input is 0 then have …0100 = ...100 (state
S6)
- If next input is 1 then have …0101 = …01 (state S2)
S
[0]
S
[0]
S
[0]
S
[0]
reset
S3 0 or 1
[1]
S
[0]
S
[0]
Exit conditions from S1: recognizes strings of form … (no 1 seen); loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form … (no 0 seen); loop back to S4 if input is 1
Finite String Pattern Recognizer
(Step 3)
- Verilog description including state assignment
(or state encoding) module string (clk, X, rst, Q0, Q1, Q2, Z); input clk, X, rst; output Q0, Q1, Q2, Z;
reg state[0:2]; ‘define S0 = [0,0,0]; //reset state ‘define S1 = [0,0,1]; //strings ending in ... ‘define S2 = [0,1,0]; //strings ending in ... ‘define S3 = [0,1,1]; //strings ending in ... ‘define S4 = [1,0,0]; //strings ending in ... ‘define S5 = [1,0,1]; //strings ending in ... ‘define S6 = [1,1,0]; //strings ending in ...
assign Q0 = state[0]; assign Q1 = state[1]; assign Q2 = state[2]; assign Z = (state == ‘S3);
always @(posedge clk) begin if rst state = ‘S0; else case (state) ‘S0: if (X) state = ‘S4 else state = ‘S1; ‘S1: if (X) state = ‘S2 else state = ‘S1; ‘S2: if (X) state = ‘S4 else state = ‘S3; ‘S3: if (X) state = ‘S2 else state = ‘S6; ‘S4: if (X) state = ‘S4 else state = ‘S5; ‘S5: if (X) state = ‘S2 else state = ‘S6; ‘S6: state = ‘S6; default: begin $display (“invalid state reached”); state = 3’bxxx; endcase
end
endmodule
Finite String Pattern Recognizer
• Review of Process
– Understanding problem
- Write down sample inputs and outputs to understand specification
– Derive a state diagram
- Write down sequences of states and transitions for sequences to be recognized
– Minimize number of states
- Add missing transitions; reuse states as much as possible
– State assignment or encoding
- Encode states with unique patterns
– Simulate realization
- Verify I/O behavior of your state diagram to ensure it matches specification
Complex Counter (State Diagram)
• Deriving State Diagram
– One state for each output combination
– Add appropriate arcs for the mode control
S
[000]
S
[001]
S
[010]
S
[011]
S
[100]
S
[101]
S
[110]
S
[111]
reset
Complex Counter (State Encoding)
• Verilog description including state encoding
module string (clk, M, rst, Z0, Z1, Z2); input clk, X, rst; output Z0, Z1, Z2;
reg state[0:2]; ‘define S0 = [0,0,0]; ‘define S1 = [0,0,1]; ‘define S2 = [0,1,0]; ‘define S3 = [0,1,1]; ‘define S4 = [1,0,0]; ‘define S5 = [1,0,1]; ‘define S6 = [1,1,0]; ‘define S7 = [1,1,1];
assign Z0 = state[0]; assign Z1 = state[1]; assign Z2 = state[2];
always @(posedge clk) begin if rst state = ‘S0; else case (state) ‘S0: state = ‘S1; ‘S1: if (M) state = ‘S3 else state = ‘S2; ‘S2: if (M) state = ‘S6 else state = ‘S3; ‘S3: if (M) state = ‘S2 else state = ‘S4; ‘S4: if (M) state = ‘S0 else state = ‘S5; ‘S5: if (M) state = ‘S4 else state = ‘S6; ‘S5: if (M) state = ‘S7 else state = ‘S7; ‘S5: if (M) state = ‘S5 else state = ‘S0; endcase
end
endmodule
Communicating Finite State
Machines
• One machine's output is another machine's
input
machines advance in lock step
initial inputs/outputs: X = 0, Y = 0
CLK
FSM
X
FSM
Y
A A B
C D D
FSM 1 FSM 2
X
Y
Y==
A
[1]
Y==
B
[0]
Y==
X==
C
[0]
X==
X==
D
[1]
X==
X==
Datapath and Control
• Digital hardware systems = data-path + control
– Datapath: registers, counters, combinational
functional units (e.g., ALU), communication (e.g.,
busses)
– Control: FSM generating sequences of control
signals that instructs datapath what to do next
"puppet"
"puppeteer who pulls the strings"
control
data-path
status
info and
inputs
control
signal
outputs
state
Implementation in Software
integer combination_lock ( ) {
integer v1, v2, v3;
integer error = 0;
static integer c[3] = 3, 4, 2;
while (!new_value( ));
v1 = read_value( );
if (v1 != c[1]) then error = 1;
while (!new_value( ));
v2 = read_value( );
if (v2 != c[2]) then error = 1;
while (!new_value( ));
v3 = read_value( );
if (v2 != c[3]) then error = 1;
if (error == 1) then return(0); else return (1);
Determining Details of the
Specification
• How many bits per input value?
• How many values in sequence?
• How do we know a new input value is entered?
• What are the states and state transitions of the
system?
value reset
open/closed
new
clock
Datapath and Control Structure
• Datapath
– Storage registers for combination values
– Multiplexer
– Comparator
• Control
– Finite-state machine controller
– Control for data-path (which value to compare)reset
open/closed
C1 C2 C3^ new
value (^) comparator equal
multiplexer
controller
mux control
clock 4
(^4 4 )
4
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State Table for Combination Lock
• Finite-State Machine
– Refine state diagram to take internal structure into
account
– State table ready for encoding
reset new equal state state mux open/closed
1 – – – S1 C1 closed
0 0 – S1 S1 C1 closed
0 1 0 S1 ERR – closed
0 1 1 S1 S2 C2 closed
0 1 1 S3 OPEN – open
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