State Machine Design with an
HDL
A methodology that works for documenting
the design, simulation and verification of the
design, and synthesis for FPGA, or a custom
ASIC generated using synthesis.
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State Machine Design with an HDL: Methodology and Style Guide, Slides of Verilog and VHDL
A methodology for documenting, simulating, verifying, and synthesizing state machine designs using an hdl, specifically for fpga or custom asic. It includes a style guide for coding state machines in an hdl, such as vhdl, verilog, or systemc, which documents well, is easily maintainable, and maps to physical logic. The style guide is demonstrated using a state machine example, the t-bird tail light problem.
Typology: Slides
2012/2013
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State Machine Design with an
HDL
A methodology that works for documenting the design, simulation and verification of the design, and synthesis for FPGA, or a custom ASIC generated using synthesis.
Lecture overview
- State machine basics
- HDL methodology
- State machine example
State Machine Basics
- Moore Machine
- Outputs are a function of the current state only Next State Logic
State Memory (F/Fs)
Output Inputs Logic^ Outputs
Current State Excitation (next state)
Moore Machine
clk
HDL code
- Coding a state machine in an HDL
- Can simply implement an algorithm
- Documents poorly
- Cannot be synthesized (possibly but less than optimal result)
- Can code for a Mealy or Moore machine in a single process
- Documents poorly
- Synthesis results are unpredictable
- Can follow a structured style
- Documents very well
- Synthesizes very well and results are predictable
- Can simply implement an algorithm
- Simulation of the three possibilities is ~ the same
Style guide
- Use a process to describe the next state logic, often in a case statement used for determination of the next state. Will see this in the example.
- Use a process to represent the latching/loading of the calculated next_state such that it becomes the current_state. This is the only process that generates sequential elements (F/Fs). The other processes represent combinational logic.
- Use a third process to represent the generation of the outputs from the current state and possibly the inputs. This process will have as its inputs, the current state and, depending on the type of state machine, the state machine inputs.
An example
- The T-Bird tail light problem
- The turn signal indicator had a light sequence on each lamp.
Design with HDL
- You still start with a state diagram
- You may or may not generate a transition
table
- Will now look at the code
- Where to start โ THE INTERFACE
- What are the inputs and the outputs?
The Entity
- Inputs are a signal for
- Right turn signal
- Left turn signal
- Hazard
- Clock
- Outputs are the signals for the lights - lc, lb, la - rc, rb, ra
The architecture
- Will use 3 processes
- Start of architecture and the process to specify the F/Fs is given here.
- Use of a state_type allow the coding to also document the design.
ARCHITECTURE state_machine OF t_bird IS TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3); SIGNAL state, next_state : state_type; BEGIN --Process to Specify F/F PROCESS BEGIN WAIT UNTIL clk=โ1โ AND clkโevent; state <= next_state; END PROCESS;
Notes on start of architecture
- Signal declaration for the state machine state
- First declare and enumeration type that has an element for each state of the state machine - Here- idle, l1,l2,l3, r1,r2,r3, lr
- Then declare signals state and next_state to be of this type. These represent the current state and the calculated next state.
- An aside: you can count the number of elements in this type to see that number of states and predict the number of F/Fs the state machine requires.
The next state process
- The second of the processes for the state machine.
- What is the next state given the current state and the state of the input signals
- Process can be of considerable size
-- Next State Logic Process PROCESS (state,lts,rts,haz) BEGIN CASE state IS WHEN idle => IF (haz=โ1โ OR (lts=โ1โ AND rts=โ1โ) THEN next_state <= lr3; ESLIF(haz=โ0โ AND (lts=โ0โ AND rts=โ1โ)) THEN next_state <= r1; ELSIF(haz=โ0โ AND (lts=โ1โ AND rts=โ0โ)) THEN next_state <= l1; ELSE next_state <= idle; END IF;
Continued on next slide
The next state process
- Continued
- Note that a case is used to switch to actions based on the current_state
- Then the value of the inputs directs the next_state for the state machine
WHEN l1 => IF (haz = โ1โ) THEN next_state <= lr3; END IF;ELSE next_state <= l2; WHEN l2 =>IF (haz = โ1โ) THEN next_state <= lr3; END IF;ELSE next_state <= l3; WHEN l3 => next_state <= idle;WHEN r1 => IF (haz = โ1โ) THEN next_state <= lr3;ELSE next_state <= r2; END IF; WHEN r2 => IF (haz = โ1โ) THEN next_state <= lr3; ELSE next_state <= r3; END IF; WHEN r3 => next_state <= idle; WHEN lr3 => next_state <= idle; END CASE; END PROCESS;
Once you have state machine description
- Simulate it in a test suite to verify the design meets specifications. This is the HDL topic of verification (ECE 764 โ even years and a terminal grad course)
- Then can synthesize the design to generate an FPGA implementation or use standard cells and generate the standard cells which can be sent to a place and route program for automatic generation of the circuit for a custom IC.
If this is done
- What would you expect
- How many F/Fs???
- For the example you would expect 3 FFs.
- Why? There are 8 states
- You could even ballpark the number of gates,