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2003/10/
Fall 2003 – Lectures 20 & 21
Serial Communications System Extensions
Memory Modeling using flowHDL
© 2003 Dr. James P. Davis
Some figures Tanenbaum, 4th^ ed. © 1999 Prentice Hall Publishers
CSCE 491CSCE 491
Capstone Computer EngrCapstone ComputerEngr. Project. Project
Lectures 20 & 21- Lectures 20 & 21- OutlineOutline
z Introduction.
9 We’re interested in the structure of memory, so that we can develop appropriate models for its functionality for use in our designs. We start with the basic structure of the memory array, then more to the architecture of the memory controller itself.
9 We will be using the memory array structure on both the Host and Peripheral sides of the serial communication model onto which we are adding functionality.
z Key Points.
9 Basic structure of the serial communications protocol is: (1) transmit data from Host to receiver on Peripheral, (2) Count data words on Peripheral side, (3) responding with a periodic “sync ACK” control word transmitted back to Host. 9 Basic structure of a memory array – From the gate level, we have an array of D-FF cells, with appropriate select logic to control when FF elements in a given row are read from and written to, so as to implement the functions of Read and Write. We’ll create two for extending the UART model.
© 2002 Dr. James P. Davis Page 3
UART Model Design Enhancements- UART Model Design Enhancements-1 1
z Add parity set (Transmitter) and parity check
(Receiver).
9 Make 8-bits the data word size, followed by parity bit, along
with start and stop bits.
9 Calculate Odd parity in both the Transmitter and Receiver
threads.
Use a sub-flowdiagram (created on a separate sheet when you place one of these objects onto the canvas). Generate the parity bit by creating the logic in the sub-flow ASM model. You will be able to use this model for both setting the parity bit (Transmitter) and testing it against an existing bit value (Receiver). Once you create this sub-flow object in the Transmitter thread, you will also be able to reference this sub-flow by (1) placing a sub-flow object on the canvas in the Receiver thread, (2) selecting the name of the “ParityGen” sub-flow from a list box.
9 The transmit and receive data registers must be modified
from 10 to 11 bits total. Check these in the Bus Table.
UART Model Design Enhancements- UART Model Design Enhancements-2 2
z Copy/paste the Controller, Receiver and Transmitter
ASM models (without the thread boundary) onto new sheets. 9 These will be the "mirror" UART on the peripheral side. 9 You'll need to add buses as appropriate, and rename some (because the control and data buses on remote side of the serial connection will be different). 9 For internal buses that hold data, simply create them with a “_2” in their name, e.g., ACC_2 for the word to transmit on the peripheral side. 9 Make sure the Host and Peripheral transmit and receive lines connect up properly (Host transmitter to Peripheral receiver, and Peripheral transmitter to Host receiver). 9 You'll simulate the connection between the two sides, so think about 2 test cases that test the “loop back” test between both ends of the serial connection: (1) transmit from Host to Peripheral receiver, (2) Transmit from Peripheral’s transmitter to Host’s receiver). You’ll make these connect up so that you don’t have to continually toggle bits in the Bus Table.
© 2002 Dr. James P. Davis Page 7
Serial Comm. System Class Diagram Serial Comm. System Class Diagram
S erialCom m unicationS y stem
H_UA RT_Ctlr (fro m Use Ca se V i e w)
U_Transm itter (fro m Use Ca se V i e w) U_Receiver (fro m Use Ca se V i e w)
P _C tlr (fro m Use Ca se V i e w) P _Rec eiver (fro m Use Ca se V ie w )
P _Transm itter (fro m Use Ca se V i e w)
M em _B uffer B uf_ID B ufRdP tr H_UA RT B ufW rP tr
HostSy stem
11
1..1..
Xm it_B uf
CP U (from Use C a se V i e w)
11 0..0..
Host Interface
Recv_B uf
Rem oteS ys tem
1..1..
11 0 ..0 ..
Com m unic atesW ith
P _UA RT
1..1..
0..0.. 0..0..
Handshak esW ith (^) P eripheral
1..1..
1..1.. 11
Pe ri ph_I ntrface
P _Rec v_B uf
Serial Comm. System Use Case DiagramSerial Comm. System Use Case Diagram
Re a d M e m W o rd In to Re g i ste r
Up d a te M e m Re a d P tr
Re a d Da ta Re g In to M e m
Up d a te M e m W ri te P tr
S e n d W o rd
S e t_ A CK _ W o rd
Re ce i ve W o rd
E n a b l e X m i t
H_ T ra n sm i tte r S e tPa ri ty^ P _ T ra n sm i tte r
Co n ca te n a te S ta rtS to p B i ts
Ch e ckP a ri ty
S trip S tar tS top B i ts
Se tP ar i tyEr ror
Co u n t_ A CK _ W o rd s
H_ UAR T _C tlr
E n a b l e UA RT
P _ Ctl r
Co u n tM e m W o rd sW ri tte n
Co u n tDa ta W o rd sRe a d
Re a d & Ch e ck_ A CK _ W o rd
H_ Re ce iv er
S i g n a l _ CP U_ Ne wW o rd
CP U
P _ Re ce i ve r
S i g na l _ Pe ri p h _Ne wW o r d
P e ri p h
This is an inventory of core partitioned system functions.
This will form the basis for defining test cases.
Each UML “actor” is Modeled using a thread.
© 2002 Dr. James P. Davis Page 9
The Gate- The Gate-level Structure of a Memory Arraylevel Structure of a Memory Array
- 4 x 3 Memory Array
- The Memory array is built up from gates and flip flops, to take advantage of certain properties of the devices. Each row is one of four 3-bit words.
- Data Lines I 0 – I 2 feed all of the D FF’s in a column. The address lines A 0 – A 1 act as select lines for a given bank.
- The control signals CS (control select), RD (read enable), OE (output enable) are used to route data to and from memory (allowing writes and reads) based on the combinational logic gates.
- The bus “drivers” are enabled by the AND of the 3 Source: Tanenbaum, 4th^ ed. © 1999, Prentice-Hall control signals.
Memory Structure and Organization Memory Structure and Organization
z m x n Memory Array
9 Memory arrays allow multi-bit values to be stored and retrieved by address. 9 A memory of n bits can be organized in different ways. 9 Memory array as a word length : the number of bits of each word stored in memory (e.g., 32 bits). 9 Memory array has number of words (e.g., 128MB). 9 Each memory location is uniquely addressable (called content addressable memory ).
Source: Tanenbaum, 4th^ ed. © 1999, Prentice-Hall
Memory Use ExampleMemory Use Example –– Memory TableMemory Table
OMemory creation consists of several steps: O(1) Create a RAM array in the Memory Table (with Addr. Width, Data Width and Type). O(2) Edit values in the array using the Matrix Table. O(3) Reference the memory locations using an index.
