UART Design: Receiving Data with FIFO and Counter, Slides of Computer Science

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UART Design

Project Thus Far

FIFO

FIFO

SRAM UARTIN

UART OUT

Main Control FSM

Collision

Audio Out interface Audio Ininterface

Packet Logic

Message Definition

• A low start bit followed by 8 data bits and a high stop bit. (clock is 250kHz)
• The wire is normally high.

Idle Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Idle

Time Figure 3 : A UART transmission.

TX

TX_E

Super-Sampling

• We watch the incoming wire at 8 times the send rate. (2MHz)
• This makes it so we can catch a 250Khz message even if its phase is different from our internal 250KHz clock.

Serial data input

Sample Here

How do I start?!?

• If the incoming message is 10 bits in length, and we super-sample at 8x, the message is complete when we receive 80 bits of data.
• How do we keep track of where I am in the message?

8-bit Binary Counter

• 3 Inputs to figure out : R, CE, C
• CE is on as long as you are receiving a new message
• C is the super-sampled clock frequency, NOT the incoming baud rate
• R is used to reset the counter once the message is complete

Clock

• You’ve seen how to divide clocks already from previous labs.
• The clock that’s available on the board already (not from the Xchecker) is 16MHz.
• Use a binary counter to divide it.
• Sticky point: You send at 250kHz, you sample at 2MHz, your circuit needs one faster than that. Probably 8MHz.

Reset

• Should be reset when the counter enable is low.
• When the RESET button on the board is pressed, the counter should reset.
• When the message is done, and DRDY goes high (data ready), this should be reset for safety/reliability reasons.
• R = CE’ + RESET + DRDY

There’s more!

• But this feedback loop will loop high forever!
• So when DRDY or RESET is asserted, PROCEED must be forced low.
• PROCEED = DRDY’ RESET’ (Q2+PROCEED)

Proceed (cont.)

Why just the last 3 bits?

• Etc.

When do we stop?

• This design uses a 8-bit shift register to save space. Thus, we don’t want the stop bit to be shifted in.
• We want to stop at 9*8+3 = 75
• 75= 01001011
• DRDY = Q6 Q3 Q2’ Q1 Q
• UART-RECEIVE IS DONE!

UART-RECEIVE (cont)

• Do not take this for granted!
• I defined the important signals, the rest are trivial.
• Make sure you UNDERSTAND the design rather than just plugging it in!

What about transmit?

• Well, you tell me.

Figure 2: UART Transmitter symbol.

UART / TX D[7:0] SEND.H RESET.H

SERIAL-OUT.H (TX)

Clock

OUTPUT_ENABLE (TX_E)

Transmitting