Understanding the Basics of Embedded Systems: Microprocessors and Instruction Cycles, Slides of Computer Science

Download Understanding the Basics of Embedded Systems: Microprocessors and Instruction Cycles and more Slides Computer Science in PDF only on Docsity!

3-Software Design Basics in

Embedded Systems

Introduction

• General-Purpose Processor

• Processor designed for a variety of computation tasks
• Low unit cost, in part because manufacturer spreads NRE over large numbers

of units

• Motorola sold half a billion 68HC05 microcontrollers in 1996 alone
• Carefully designed since higher NRE is acceptable
• Can yield good performance, size and power
• Low unit cost, short time-to-market/prototype, high flexibility
• User just writes software; no processor design
• a.k.a. “microprocessor” – “micro” used when they were implemented on one

or a few chips rather than entire rooms

Data-path Operations

• Load
  • Read memory location into

register

• ALU operation

• Input certain registers through ALU, store back in register

• Store

• Write register to memory location

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

Control Unit

• Control unit: configures the datapath

operations

• Sequence of desired operations (“instructions”) stored in memory – “program”
• Instruction cycle – broken into several sub-

operations, each one clock cycle, e.g.:

• Fetch: Get next instruction into IR
• Decode: Determine what the instruction means
• Fetch operands: Move data from memory to datapath register
• Execute: Move data through the ALU
• Store results: Write data from register to memory

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

R0 R

Control Unit Sub-Operations

• Decode

• Determine what the

instruction means

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

(^100) load R0, M[500] R0 R

Control Unit Sub-Operations

• Fetch operands

• Move data from memory

to data-path register

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

(^100) load R0, M[500] R0 R

Control Unit Sub-Operations

• Store results

• Write data from register

to memory

• This particular instruction

does nothing during this

sub-operation

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

(^100) load R0, M[500] R0 R

Instruction Cycles

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

R0 R

PC= 100

Fetch

ops

Exec. Store

results

clk

Fetch

load R0, M[500]

Decode

Instruction Cycles

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status

load R0, M[500] (^) 500

501

101 inc R1, R 102 store M[501], R

R0 R

PC= 100

Fetch Decode Fetch

ops

Exec. Store

results

clk

PC= 101

Fetch Decode Fetch

ops

Exec. Store

results

clk

PC= 102

store M[501], R

Fetch Fetch

ops

Exec.

Store

results

clk

Decode

Architectural Considerations

• N-bit processor

• N-bit ALU, registers, buses,

memory data interface

• Embedded: 8-bit, 16-bit, 32-

bit common

• Desktop/servers: 32-bit,

even 64

• PC size

determines

address space

Processor Control unit Datapath

ALU

Registers

PC IR

Controller

Memory

I/O

Control /Status