ECE 2030 Exam III: Electrical Eng. Exam on State Machines, Flip Flops, and Counters, Exams of Computer Science

A past exam from ece 2030, a course in electrical engineering. The exam covers various topics including state machines, flip flops, and counters. Students are required to answer multiple-choice and problem-solving questions. The exam includes 5 questions with a total of 65 points. Questions range from designing gate-level diagrams of latches, understanding the difference between mealy and moore state machines, and designing up/down saturating counters.

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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ECE 2030
Section C
Exam III
November 5th, 2008
2:05 pm 2:55 pm
1. The Georgia Tech Honor Code governs this examination.
2. There are 5 questions and 9 pages including two blank worksheets. Make sure you have all of them.
3. Please write/draw legibly. Use the work sheets for generating the solutions before providing the
final answer.
4. State any assumptions you feel you have to make or ask for clarification
5. Keep in mind it is difficult to give partial credit without written material. Please make sure you
document any partial solutions.
6. Problems are weighted according to the chart below. Plan your work!
7. The exam is 50 minutes.
Problem Max Points Graded
1 25
2 10
3 10
4 10
5 10
Total 65
Student Name: __________________________________
Student Number: ________________________________
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ECE 2030

Section C

Exam III

November 5

th

2:05 pm 2:55 pm

  1. The Georgia Tech Honor Code governs this examination.
  2. There are 5 questions and 9 pages including two blank worksheets. Make sure you have all of them.
  3. Please write/draw legibly. Use the work sheets for generating the solutions before providing the final answer.
  4. State any assumptions you feel you have to make or ask for clarification
  5. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 6. Problems are weighted according to the chart below. Plan your work! 7. The exam is 50 minutes.

Problem Max Points Graded 1 25 2 10 3 10 4 10 5 10 Total 65

Student Name: __________________________________

Student Number: ________________________________

  1. ( 25 pts ) This question covers all of the modules on this exam. a. Consider a state machine that has 11 states. How many flip flops are necessary for its implementation.

b. Draw a gate level diagram of an SR latch with enable.

c. Which function represents the aymptotic delay of a carry look-ahead adder?

  1. linear
  2. logarithmic
  3. quadratic
  4. constant

d. Provide the truth table of a full adder. Make sure it is clear what the inputs and outputs are.

  1. ( 10 pts ) Fill in the timing of A, B & C. Assume all registers and latches are initialized to 0.

Reg Latch Reg

IN A B C

IN

A

B

C

  1. ( 10 pts ) You wish to design an up/down saturating counter for the range 0-7. This is a counter that does not “roll” over when counting up or down. For example when counting up, when it reaches 7 rather than rolling over it stays at 7. a. Show the state diagram. Make sure you clearly label all states, inputs and outputs.

b. Provide the corresponding state transition table. Make sure your encoding choices are clear.

  1. ( 10 pts ) You are given the 4-bit up-counter below as a building block. TE is the toggle enable and internally it is constructed using toggle cells. Using any additional gates and building blocks as necessary construct a two digit seconds counter, i.e., it can count from 0-59 before rolling over to 0.

4-bit Counter

Q 3 Q 2 Q 1 Q 0

TE

CLEAR