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A past exam from ece 2030, a course in electrical engineering. The exam covers various topics including state machines, flip flops, and counters. Students are required to answer multiple-choice and problem-solving questions. The exam includes 5 questions with a total of 65 points. Questions range from designing gate-level diagrams of latches, understanding the difference between mealy and moore state machines, and designing up/down saturating counters.
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Problem Max Points Graded 1 25 2 10 3 10 4 10 5 10 Total 65
Student Name: __________________________________
Student Number: ________________________________
b. Draw a gate level diagram of an SR latch with enable.
c. Which function represents the aymptotic delay of a carry look-ahead adder?
d. Provide the truth table of a full adder. Make sure it is clear what the inputs and outputs are.
Reg Latch Reg
b. Provide the corresponding state transition table. Make sure your encoding choices are clear.
4-bit Counter
CLEAR