Fall 2001 Comp Eng Exam Solutions: SRAM, State Machine, Multiplexer, Microcode., Exams of Computer Science

The solutions to exam three for the computer engineering course in fall 2001. It includes the solutions to four problems covering topics such as sram memory cell design, state machine design, multiplexer and shifter design, and microcode reverse engineering.

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Uploaded on 04/08/2013

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ECE 2030 10:00am Computer Engineering Fall 2001
4 problems, 4 pages Exam Three Solutions 28 November 2001
1
Problem 1 (3 parts, 30 points) Memory Systems
This problem examines a 16 Mbit SRAM chip organized as 2 million addresses of 8-bit words.
Part A (10 points) Draw an SRAM memory cell. Label the signals D, -D, and Select.
DD
S
Part B (10 points) Suppose both the SRAM cell and the SRAM chip are square. Using the
organization approach discussed for DRAM, answer the following questions about the chip.
number of columns KM 42216 1224 ===
number of words per column 512222 9312 ==
column decoder required (n to m)12 to 4K
number of muxes required 8
Part C (10 points) Consider 8 million addresses of 128-bit words SRAM memory system.
number of chips needed in one bank 128 / 8 = 16
number of banks for memory system 8M / 2M = 4
memory decoder required (n to m)2 to 4
number of SRAM chips required 16 x 4 = 64
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4 problems, 4 pages Exam Three Solutions 28 November 2001

Problem 1 (3 parts, 30 points) Memory Systems

This problem examines a 16 Mbit SRAM chip organized as 2 million addresses of 8-bit words.

Part A (10 points) Draw an SRAM memory cell. Label the signals D, -D, and Select.

D D

S

Part B (10 points) Suppose both the SRAM cell and the SRAM chip are square. Using the organization approach discussed for DRAM, answer the following questions about the chip.

number of columns (^16) M = 224 = 212 = 4 K

number of words per column (^2 12 23) = 29 = 512

column decoder required ( n to m ) 12 to 4K

number of muxes required 8

Part C (10 points) Consider 8 million addresses of 128-bit words SRAM memory system.

number of chips needed in one bank 128 / 8 = 16

number of banks for memory system 8M / 2M = 4 memory decoder required ( n to m ) 2 to 4 number of SRAM chips required 16 x 4 = 64

4 problems, 4 pages Exam Three Solutions 28 November 2001

Problem 2 (2 parts, 20 points) State Machine

Part A (15 points) Using the following state table, complete the state diagram below. Use correct state diagram notation. S variables are the current state. NS variables are the new state. X and Y are inputs while A is an output.

S 1 S 0 Y X NS 1 NS 0 A S 1 S 0 Y X NS 1 NS 0 A 0 0 X 0 0 0 0 1 0 X 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 X 0 0 1 0 1 1 X 0 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1

Part B (5 points) Suppose the primary output of this state machine is S 1 and S 0. Briefly describe what this state machine does.

The state machine is an up/ down counter

4 problems, 4 pages Exam Three Solutions 28 November 2001

Problem 3 (5 parts, 25 points) Microcode Reverse Engineering

The microcode fragment below runs on the datapath discussed in class (see exam handout). For each part below, answer the question asked about the microcode execution. Don’t care values (X) have been converted to zeros. For maximum credit, be as specific and concise as you can (e.g., list shift types, amounts, and directions, logical functions, memory addresses and operations, etc.)

cycle X Y Z rwe im en im va au en -a/s lu en lf su en st ld en st en r/-w msel 1 0 0 1 1 1 8765 0 0 1 C 0 0 0 0 0 0 2 1 0 1 1 1 FFF0 0 0 0 0 1 0 0 0 0 0 3 1 0 1 1 1 4321 0 0 1 E 0 0 0 0 0 0 4 1 0 2 1 0 0 0 0 0 0 0 0 1 0 1 1 5 1 0 1 1 1 0010 0 0 0 0 1 2 0 0 0 0 6 1 0 3 1 0 0 0 0 0 0 0 0 1 0 1 1 7 2 3 4 1 0 0 1 1 0 0 0 0 0 0 0 0 8 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Part A (5 points) What value is stored in register 1 following cycle 2 (in hexadecimal)?

87650000 Part B (5 points) What memory location is accessed during cycle 4 (in hexadecimal)?

87654321 Part C (5 points) What memory location is accessed during cycle 6 (in hexadecimal)?

43218765 Part D (5 points) Describes the operation that occurs during cycle 7 (be specific).

R4 ← R2 – R

Part E (5 points) Describes the operation that occurs during cycle 8 (be specific).

[R1 (43218765)]R