Procedures and Functions in VHDL: Declaration, Calling, and Parameters, Slides of Computer Science

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Subprograms

Subprograms

• When we write complex behavioral model it is

useful to divide the code into sections, each

dealing with a relatively self-contained part of

behavior  VHDL provides subprograms

facility

• VHDL Subprogram:

• procedures
• functions

Procedures

• EBNF of Procedure call: page 197

• Example:

average_samples;

Procedures

• A procedure declaration can be written in

declarative part of a process or an architecture

body

• Procedures in a process can be called only in

the process body.

• Procedures in an architecture body can be

called by the processes in the architecture

body

architecture rtl of control_processor is

--...

begin

alu : process is procedure do_arith_op is begin -- …; end procedure do_arith_op; begin --... do_arith_op; --...

end process alu;

instruction_interpreter : process is variable mem_address_reg, mem_data_reg, prog_counter, instr_reg, accumulator, index_reg : word; --... procedure read_memory is begin address_bus <= mem_address_reg; mem_read <= '1'; mem_request <= '1'; wait until mem_ready = '1'; mem_data_reg := data_bus_in; mem_request <= '0'; wait until mem_ready = '0'; end procedure read_memory; begin -- …. end process instruction_interpreter;

Figure 7. A procedure is called several times in a process

Procedures

• A procedure call is a form of sequential

statement and a procedure body implements

an algorithm using sequential statements

• A procedure can call another procedures

• Example: next page

control_sequencer : process is procedure control_write_back is begin wait until phase1 = '1'; reg_file_write_en <= '1'; wait until phase2 = '0'; reg_file_write_en <= '0'; end procedure control_write_back; procedure control_arith_op is begin wait until phase1 = '1'; A_reg_out_en <= '1'; B_reg_out_en <= '1'; wait until phase1 = '0'; A_reg_out_en <= '0'; B_reg_out_en <= '0'; wait until phase2 = '1'; C_reg_load_en <= '1'; wait until phase2 = '0'; C_reg_load_en <= '0'; control_write_back; -- call procedure end procedure control_arith_op;

Figure 7. A procedure calls another procedure

Return statement in a Procedure

• EBNF of return statement: see page 201

• Return statement is useful to return from the

middle of a procedure (ex. Exception)

• Example:

instruction_interpreter : process is procedure read_memory is begin address_bus <= mem_address_reg; mem_read <= '1'; mem_request <= '1'; wait until mem_ready = '1' or reset = '1'; if reset = '1' then return; end if; mem_data_reg := data_bus_in; mem_request <= '0'; wait until mem_ready = '0'; end procedure read_memory; begin loop … read_memory; exit when reset = '1'; … end loop; end process instruction_interpreter;

Figure 7. A procedure with return statement

procedure do_arith_op ( op : in func_code ) is

variable result : integer; begin case op is when add => result := op1 + op2; when subtract => result := op1 - op2; end case; dest <= result after Tpd; Z_flag <= result = 0 after Tpd;

end procedure do_arith_op;

…

do_arith_op ( add );

…

Figure 7. A parameterized procedure

procedure addu ( a, b : in word32; result : out word32; overflow : out boolean ) is variable sum : word32; variable carry : bit := '0'; begin for index in sum'reverse_range loop sum(index) := a(index) xor b(index) xor carry; carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) ); end loop; result := sum; overflow := carry = '1';

end procedure addu;

…

addu ( PC, X"0000_0004", next_PC, overflow_flag);

…

Figure 7. A parameterized In-mode procedure

a, b : constant Result, overflow: variable Docsity.com

procedure receive_packet ( signal rx_data : in bit; signal rx_clock : in bit; data_buffer : out packet_array ) is begin for index in packet_index_range loop wait until rx_clock = '1'; data_buffer(index) := rx_data; end loop; end procedure receive_packet;

begin

packet_assembler : process is variable packet : packet_array; begin --... receive_packet ( recovered_data, recovered_clock, packet ); --... end process packet_assembler;

Figure 7. A procedure With signal parameters

Signal parameter: Pass by reference Variable parameter: Pass by value

library ieee; use ieee.std_logic_1164.all;

architecture top_level of signal_generator is

signal raw_signal : std_ulogic; --... procedure generate_pulse_train ( width, separation : in delay_length; number : in natural; signal s : out std_ulogic ) is begin for count in 1 to number loop s <= '1', '0' after width; wait for width + separation; end loop; end procedure generate_pulse_train;

begin

-- next page

end architecture top_level;

Figure 7. A procedure With signal parameters

Signal parameter: Pass by reference Variable parameter: Pass by value