VHDL Subprograms: Functions and Procedures, Study notes of Electrical and Electronics Engineering

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VHDL in Action

Chapter 3

Subprograms

pp. 90-

ECE 4514 Martin 2003 2

Subprograms

z Why have subprograms?

• Design re-use, Sharing, Readability

z Subprogram issues:

• How do subprograms execute with respect to simulation time? - Wait statements? - Signal assignments? - Concurrent vs. sequential subprograms

z Two types of subprograms:

• Functions
• Procedures

ECE 4514 Martin 2003 3

VHDL Subprograms

z Classes of subprograms

• Function

• Computes and returns a value
• Does not modify any arguments
• Used only in expressions

• Procedure

• May modify its arguments
• Does not return a value
• Sequential or Concurrent Statement ECE 4514 Martin 2003 4

Ports and Subprogram

Parameters

z Port modes define how signals

connect to an entity:

• IN information flows into entity
• OUT information flows out of entity
• INOUT information flows into and out of entity
• BUFFER information flows into and out of entity
• LINKAGE information flows into and out of entity

z Subprogram interface parameters

are similar to ports

Interface Parameter of

mode OUT

z OUT parameters can only be assigned:

entity FOO is

port (D: out Boolean);

end FOO;

architecture BLAH of FOO is

signal E: Bit;

begin

D <= 5 > 3 ; -- This is correct.

E <= ' 1 ' when D else ' 0 '; -- This is an error.

end BLAH;

Constraints on Declarations

of Parameters

z Mode IN - Constants or Signals

z Mode OUT - Variables or Signals

z Mode INOUT - Variables or Signals

z All PORTS in entities must be

signals

ECE 4514 Martin 2003 7

Functions

z To declare a function in VHDL, specify:

• the name of the function
• the input parameters (if any) (formal parameters)
• the type of the returned value
• any declarations required by the function
• an algorithm for the computation of the returned

value

ECE 4514 Martin 2003 8

Functions

z Declare in architecture declaration

section:

architecture WITHFUNCTION of WHAT is

<declare function(s) here>

begin

< call functions here>

end;

ECE 4514 Martin 2003 9

Structure for Function

Body Specification

function function_name ( function_formal_parameter_list )

return return_type is

function_declaration_part

begin

sequential_statements

return ( return_value );

end function_name ;

z CONSTRAINT: All parameters in the function formal

parameter list must have mode IN.

z No signals allowed in the function declaration part.

No WAIT statements allowed either directly or indirectly.

ECE 4514 Martin 2003 10

Function Example

z Type conversion: Bit_vector to Integer:

function BV2INT ( BVIN:Bit_vector( 7 downto 0 )) return Integer is variable TEMP: Integer := 0 ; begin for i in 0 to 7 loop if BVIN(i) = ' 1 ' then TEMP := TEMP + 2**i; end if; end loop; return TEMP; end BV2INT;

Variables in functions

are dynamic.

Another Function Body

function DECODE3TO8 ( V: Bit_vector ( 2 downto 0 )) return Bit_vector is variable RESULT: Bit_vector( 7 downto 0 ) := "00000001"; begin if v(0) = ' 1 ' then RESULT := RESULT(6 downto 0) & ' 0 '; end if; if v(1) = ' 1 ' then RESULT := RESULT(5 downto 0) & " 00 "; end if; if v(2) = ' 1 ' then RESULT := RESULT(3 downto 0) & " 0000 "; end if; return RESULT; end DECODE3TO8;

Formal

Using Functions

architecture FPGA of CONTROL_UNIT is insert function definition here signal IAREG, IBREG, ICREG: Bit_vector(9 downto 0); signal AREGSEL, BREGSEL, CREGSEL: Bit_vector(2 downto 0); begin

IAREG <= "00" & DECODE3TO8( AREGSEL ); IBREG <= "00" & DECODE3TO8( BREGSEL ); ICREG <= "00" & DECODE3TO8( CREGSEL ); o o o

Actuals

ECE 4514 Martin 2003 13

Function Example

architecture BEHAV of DFF is signal CLK: Bit; function RISING_EDGE (signal CLOCK: Bit ) return Boolean is variable EDGE: Boolean; begin EDGE := (CLOCK=' 1 ' and CLOCK'event ); return( EDGE ); end RISING_EDGE; begin o o

Formal

ECE 4514 Martin 2003 14

Function Example

(cont'd)

begin

Fred: process

begin

wait until (RISING_EDGE(CLK));

q <= d after 5 ns;

end process Fred;

end behav;

Actual

ECE 4514 Martin 2003 15

Another example

z Functions can even be used for delays:

function delay(value: bit; phl: time; plh: time) return time is begin if value = '1' then return plh; else return phl; end if; end delay;

z Then elsewhere:

A <= B and C after delay(B and C, 16 ns, 10 ns); ECE 4514 Martin 2003 16

Function Usage

z Rules for functions:

• The only allowable mode for

parameters is in.

• The only allowed object classes

are constant or signal.

• If the object class is not specified,

it is assumed to be constant.

Procedures

z PROCEDURES are subprograms that can

modify one or more of the input

parameters.

z Parameters may be of mode IN, OUT or

INOUT.

z If the class of a parameter is not explicitly

declared, it is assumed that:

• INs are assumed to be of class CONSTANT
• OUTs and INOUTs are assumed to be VARIABLE

Procedures (cont'd)

z As with functions, type of formal in

declaration must match type of actual

when called.

z Variables declared within a procedure are

initialized on each procedure call and

values do not persist across invocations of

the procedure.

Variables declared within procedures are dynamic.

ECE 4514 Martin 2003 19

Procedures

z To declare a PROCEDURE in VHDL,

specify:

• the name of the procedure
• the input and output parameters (if any)
• any declarations required by the

procedure itself

• an algorithm

ECE 4514 Martin 2003 20

Structure for Procedure

Body Specification

procedure procedure_name ( procedure_parameter_list ) is

procedure_declaration_part

begin

sequential_statements

end procedure_name ;

z Parameters in the procedure formal parameter list may

have mode IN, OUT, or INOUT.

z No signals allowed in the procedure declaration part.

ECE 4514 Martin 2003 21

Example Procedure (1 of 3)

procedure ADSU16P (signal A : in Bit_vector(15 downto 0); signal B : in Bit_vector(15 downto 0); signal CIN : in Bit; signal ADD : in Bit; signal S : out Bit_vector(15 downto 0); signal OFL : out Bit) is variable MS : Bit_vector ( 15 downto 0 ); variable MB : Bit_vector ( 15 downto 0 ); variable CARRY : Bit; begin o

Formals

Internal variables visible only inside procedure.

ECE 4514 Martin 2003 22

Example (2 of 3)

begin

if ADD = ' 1 ' then

CARRY := CIN;

MB := B;

else

CARRY := not CIN;

for i in 0 to 15 loop

MB(i) := not B(i);

end loop;

end if;

Example (3 of 3)

for i in 0 to 15 loop MS(i) := MB(i) xor (A(i) xor CARRY); CARRY := (MB(i) and A(i)) or ( (MB(i) and CARRY) or (A(i) and CARRY)); end loop; -- compute overflow bit if (MB(15) = A(15)) then OFL <= MB(15) xor MS(15); else OFL <= ' 0 '; end if; S <= MS; end ADSU16P;

Using Procedures

z Signals cannot be declared in

procedures

z Ports are visible within procedures

z Can have WAITs in procedure **

ECE 4514 Martin 2003 25

Observations

z Procedures can be called as

concurrent statements or as

sequential statements within a

process.

ECE 4514 Martin 2003 26

Procedure Usage

z Rules for procedures:

• The allowable modes for parameters are

in, out, and inout

• The allowable object classes depend on

the mode of the parameter.

• If the mode is in and if no object class is

specified, then constant is assumed

• If the mode is inout or out and if no

object class is specified, then variable is

assumed.

ECE 4514 Martin 2003 27

Subprogram Overloading

z Same function name can be

used to identify a variety of

functions or procedures

z Names are the same, but differ

in:

• number of parameter arguments

• types of individual parameters

ECE 4514 Martin 2003 28

Overload Example

z These all have different types:

function "and" ( ARG1, ARG2 : Bit ) return Bit;

function "and" ( ARG1, ARG2 : Bit_vector) return

Bit_vector;

function "and" (ARG1, ARG2 : Std_logic ) return

Std_logic;

function "and" (ARG1, ARG2 : Signed ) return Signed;

function "and" (ARG1, ARG2 : COLOR ) return COLOR;

Overload Example

z Different number of parameters:

DFF ( CLK, D, Q );

DFF ( CLK, D, Q, QBAR);

DFF ( CLK, D, CLEAR, PRESET, Q );

z Cannot have both the same

number of parameters and the

same types for parameters

DFF ( CLK, D, CLEAR, Q, QBAR );

DFF ( CLK, D, PRESET, Q, QBAR );

All signals in this example are assumed to be of type BIT

Overloading Example 2b

z Overloading by type:

architecture OLOAD is

signal A, B, Z : Bit;

signal AV, BV, ZV : Bit_vector(3 downto 0);

begin

Z <= A and B;

ZV <= AV and BV;

.

.

ECE 4514 Martin 2003 31

More Overloads

z Can also overload other built-in

operators:

• +

function "+" (A, B : COLOR) return COLOR;

• *

function "*" (A, B : Std_logic_vector) return

Std_logic_vector;

ECE 4514 Martin 2003 32

Subprogram visibility

ECE 4514 Martin 2003 33

Summary

z Two types of subprograms:

• Functions

• Return a single value, cannot modify

inputs

• No side effects

• Procedures

• Can return multiple values, modify inputs
• May have side effects