The Intel Microprocessor Solution Manual 8th Edition, Study Guides, Projects, Research of Microprocessors

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Online Instructor’s Manual

to accompany

Intel Microprocessors

Eighth Edition

Barry B. Brey

Upper Saddle River, New Jersey Columbus, Ohio

Copyright © 2009 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458. Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. For information regarding permission(s), write to: Rights and Permissions Department. Pearson Prentice Hall™ is a trademark of Pearson Education, Inc. Pearson®^ is a registered trademark of Pearson plc Prentice Hall®^ is a registered trademark of Pearson Education, Inc. Instructors of classes using Barry B. Brey’s, The Intel Microprocessors, may reproduce material from the instructor’s manual for classroom use. 10 9 8 7 6 5 4 3 2 1 ISBN-13: 978-0-13-504973- ISBN-10: 0-13-504973-

Chapter One

1. Charles Babbage
2. Herman Hollerith
3. To decode the Enigma code during World Was II
4. Intel Corporation
5. Grace Hopper
6. 8080
7. 8086/
8. 4G bytes
9. 1995
10. 80486 through the Core
11. Complex Instruction Set Computer
12. 1024
13. 1024
14. 1,000,
15. 2G or 3G for 32-bit mode and currently 8G for 64-bit mode
16. 1G
17. Currently 1T byte using a 40-bit address
18. Protected memory or extended memory
19. An early operating system called the Disk Operating System
20. Video Electronics Standards Association
21. Universal Serial Bus
22. Extended Memory System
23. System Area
24. The BIOS controls the computer at its most basic level and provides for compatibility between computers.
25. The microprocessor is the controlling element in a computer system.
26. Address bus
27. The I/O read signal causes an I/O device to be read.
28. (a) defines a byte or bytes of memory (b) defines a quadword or quadwords of memory (c) defines a word or words of memory (d) defines a doubleword or doublewords of memory
29. (a) 13.25 (b) 57.1875 (c) 43.3125 (d) 7.
30. (a) 163.1875 (b) 297.75 (c) 172.859375 (d) 4011.1875 (e) 3000.
31. (a) 0.101 0.5 0.A (b) 0.0000101 0.024 0.0A (c) 0.10100001 0.502 0.A (d) 0.11 0.6 0.C (e) 0.1111 0.74 0.F
32. (a) C2 (b) 10FD (c) BC (d) 10 (e) 8BA
33. (a) 0111 1111 (b) 0101 0100 (c) 0101 0001 (d) 1000 0000
34. (a) 46 52 4F 47, (b) 41 72 63, (c) 57 61 74 65 72, and (d) 57 65 6C 6C
35. The Unicode is the 16-bit alphanumeric code used with Windows
36. (a) 0010 0000 (b) 1111 0100 (c) 0110 0100 (d) 1010 0100
37. DB -

A

B

1. (a) (b) (c)
2. DW 1234H
3. (a) –128 (b) 51 (c) –110 (d) –
4. (a) 0 01111111 10000000000000000000000 (b) 1 10000010 01010100000000000000000 (c) 0 10000101 10010001000000000000000 (d) 1 10001001 00101100000000000000000

Chapter Two

1. Program visible register are the registers that are directly used in an instruction.
2. The 80386 through the Core
3. CL, CX, ECX, or RCX
4. INC and DEC
5. Odd
6. The 80386 through the Core
7. (a) 10000H—1FFFFH (b) 12340H—2233FH (c) 23000H—32FFFH (d) E0000H—EFFFFH (e) AB000H—BAFFFH
8. 100000H
9. EAX, EBX, ECX, EDX, EBP, ESI, and EDI
10. Stack
11. (a) 23000H (b) 1C000H (c) CA000H (d) 89000H (e) 1CC90H
12. Any location in the memory system
13. 8,
14. 01000000H—0100FFFFH
15. 4
16. Descriptor 20H, local table, a privilege ring 1
17. GDTR
18. The internal cache is loaded with the base address, offset address, and access rights byte
19. The GDTR address the Global Descriptor Table 41.4,
20. 4M
21. 30000000H
22. The flat mode memory system is used with 64-bit operation of the Core

17. CS

1. EAX, EBX, ECX, EDX, ESP, EBP, EDI and ESI
2. The BH register is moved to memory location 020FFH and the BL register is moved to location 020FEH then SP is changed to 00FEH.
3. 2
4. The MOV DI,NUMB instruction copies the 16-bit number in the data segment location NUMB into DI while the LEA DI,NUMB loads DI with the offset address of location NUMB.
5. The MOV with the OFFSET directive
6. LDS loads DS and LSS loads SS along with another 16-bti register for the offset address
7. If the direction flag is cleared it selects auto-increment for the string instructions and if the direction flag is set is selects auto-decrement.
8. MOVS
9. A 4-bit number is loaded into RAZ from the data segment memory location addressed by ESI and then ESI is either incremented or decrement by 8 depending on the setting of the direction flag.
10. The STOSW instruction copies AX into the extra segment memory location addressed by DI then DI is either incremented or decremented by two as dictated by the direction flag.
11. The REP prefix repeats a string instruction CX number of times.
12. DX register
13. TABLE DB 30H, 31H, 32H, 33H DB 34H, 35H, 36H, 37H, 38H, 39H BCD2A PROC NEAR MOV BX,OFFSET TABLE XLAT RET BCD2A ENDP
14. IN AL, 12H copies the byte from I/0 device 12H into AL
15. The segment override prefix allows the default segment to be changed to any segment
16. XCHG AX, BX XCHG ECX, EDX XCHG SI, DI
17. DX is copied into CX if a not zero or not equal condition exists.
18. LIST1 DB 30 dup(?)
19. The .686 directive informs the assembler that a Pentium Pro or newer microprocessor is the target of the assembled program.
20. models
21. The program terminates and control is passed back to the operating system.
22. The uses directive specifies which registers are saved on the stack at the beginning of a procedure and popped at the end of the procedure.
23. If the model statement precedes the processor directive the code generated is 16- bit.

Chapter Five

1. (a) ADD AX,BX (b) ADD AL,12H (c) ADD EBP,EDI (d) ADD CX,22H (e) ADD AL,[SI] (f) ADD FROG,CX (g) ADD RCX,234H
2. No instruction is available to add to a segment register.
3. ADD AH,AL ADD AH,BL ADD AH,CL ADD AH,DL MOV DH,AH
4. MOV EDI,ECX ADD EDI,EDX ADD EDI,ESI
5. ADC DX,BX
6. The instruction does not specify the size of the data addressed by BX and can be corrected with a BYTE PTR, WORD PTR, DWORD PTR, or QWORD PTR.
7. DL = 81H, S = 1, Z = 0, C = 0, A = 0, P = 0, O = 1
8. DEC EBX
9. Both instructions subtract, but compare doe not return the difference, it only changes the flag bits to reflect the difference.
10. AH contains the most significant part of the result and AL contains the least significant part of the result.
11. EDX and EAX as a 64-bit product
12. IMUL is signed multiplication while MUL is unsigned.
13. AX
14. RAX
15. IDIV is seined division, while DIV is unsigned division.
16. RAX
17. DAA and DAS
18. AAA, AAS, AAD, and AAM
19. PUSH AX MOV AL,BL ADD AL,DL DAA MOV AL,BH ADC AL,DH DAA MOV BX,AX POP AX ADC AL,CL DAA XCHG AH,AL ADC AL,CH DAA XCHG AH,AL
20. (a) AND BX,DX (b) AND DH,0EAH (c) AND DI,BP (d) AND EAX,1122H (e) AND [BP],CX (f) AND DX,[SI–8] (g) AND WHAT,AL
21. (a) OR AH,BL (b) OR ECX,88H (c) OR SI,DX (d) OR BP,1122H

1. An infinite loop is created.
2. A .BREAK can be used to break out of a .WHILE construct.
3. The main difference between a near and a far call is the distance from the call and the type of call and return that assembles.
4. The near return retrieves the return address from the stack and places it into the instruction address register.
5. PROC
6. The RET 6 deletes 6 bytes from the stack before returning from a procedure.
7. SUMS PROC NEAR MOV EDI, ADD EAX,EBX JNC SUMA MOV EDI, SUMS1: ADD EAX,ECX JNC SUMS MOV EDI, SUMS2: ADD EAX,EDX JNC SUM MOV EDI, SUMS3: SUMS ENDP
8. INT
9. An interrupt vector contains the offset address followed by the segment address in 4 bytes of memory.
10. The IRETD instruction pops the flags, a 32-bit offset address, and the protected mode selector for the CS register.
11. The IRETQ instruction is used in the 64-bit mode to return from an interrupt service procedure.
12. 100H—103H
13. WAIT
14. 16
15. ESC

Chapter Seven

1. No, macro sequences and dot commands are not supported by the inline assembler.
2. Labels are defined in the inline assembler exactly as they are in the assembler.
3. EAX
4. Dot commands are not usable in the inline assembler.
5. The program uses SI and SI is not saved by the inline assembler so it must be saved and restored using a PUSH and POP.
6. The main difference is that when using the 16-bit version a program should attempt to use only 8- and 16- bit registers, while when using the 32-bit version a program should attempt to use 8- and 32-bit registers.
7. The conio header allows the putch() getche() functions to be used in a program.

1. Embedded applications use different I/O than the PC so the conio library would not be used in an embedded application.
2. The disp procedure divides by the number base and saves the remainders to generate a number in any number base.
3. The PUBLIC statement identifies a label as being available outside of the module.
4. It defines that the GetIt function has a single integer passed to it and returns nothing.
5. A control is usually some visible object that is obtained from the tool box in most cases.
6. It is a 32-bit pointer.
7. External procedures are defined using the extern prototype.
8. It uses a 32-bit (DWORD) number.
9. int RotateLeft3 (int number) { if ( ( number & 0x20000000 ) == 0x20000000 ) { number <<= 3; number |= 1; } else number <<= 3; return number; }
10. The green arrow is clicked in the development environment.
11. An ActiveX control is a control such as an edit box or textbox used to build a visual application.

Chapter Eight

1. Object
2. Library
3. EXTRN indicates that a label is outside of the current program module.
4. Only the function used from the library file are placed in a program.
5. A macro sequence is a short list of instruction placed in a program when the macro is invoked.
6. ADD32 MACRO ADD AX,CX ADC BX,DX ENDM
7. ADDLIST MACRO PARA1,PARA PUSH AX PUSH DI PUSH SI PUSH BX MOV BX,OFFSET PARA MOV DI,PARA .REPEAT MOV AL,[DI] ADD AL,[BX]

1. Subtract 30 from each digit, multiply the result (initial value of 0) by 10, add a digit, and continue this for all three digits.
2. char GetIt (char temp) { char lookup[] = {’0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’, ’8’,’9’,’A’,’B’,’C’,’D’,’E’,’F’}; return lookup[temp]; }
3. The master file table contains descriptors that describe the location of the file or folder.
4. The boot record (track zero, sector zero) contains the bootstrap loader program. The bootstrap loader program loads the operating system from the disk into the system.
5. 4K
6. Unicode
7. 3
8. String^ fileName = "C:\Test1.txt"; array^ Array = gcnew array(512); try { FileStream^ fs = File::OpenRead(fileName); fs->Read(Array, 0, 512); fs->Close(); } catch (...) { MessageBox::Show("Disk error"); Application::Exit(); }
9. The remove function removes a file or folder from the disk.

Chapter Nine

1. The main differences are the data bus width and the (^) IO / M signal.
2. (a) 1 (b) 5 (c) 5
3. These bits indicate the segment being addressed by the current instruction.
4. The WAIT instruction waits for the (^) TEST pin to become a logic zero.
5. Maximum mode
6. Never
7. During a HOLD, the microprocessor stops processing instructions and places the address, data, and controls buses at the high-impedance state.
8. The (^) LOCK pin becomes a logic zero during instructions that pre prefixed with the LOCK: prefix.
9. The clock signal is provided, the RESET input is synchronized, and the READY input is synchronized.

1. EFI input
2. zero
3. Address/Data bus
4. The (^) BHE signal is shared with a status bit (S7).
5. (^) DT / R
6. 1.0 μs
7. 2.5 MIPS
8. 600 ns – 110 ns – 30 ns = 460 ns
9. ∞
10. 0
11. It generates system control signals

Chapter Ten

1. All memory devices have address, data, and control connections.
2. (a) 2048 four bit numbers (b) 1024 one bit numbers (c) 4096 eight bit numbers (d) 16,384 one bit numbers (e) 65,536 four bit numbers
3. It causes the memory device to read data from a location.
4. (a) 1K (b) 2K (c) 4K (d) 8K (e) 128K
5. Flash memory requires an extended amount of time to accomplish an erase and write.
6. The (^) G input cause a read, the (^) W input causes a write, and the (^) S input selects the chip.
7. Dynamic random access memory.
8. These inputs strobe the column and row addresses into a DRAM.
9. Memory rarely fills the entire memory, which requires some form of decoder to select the memory device for a specific range of memory addresses.

A 0 - - A 1 4 U 3 A T 2 7 2 5 6 1 0 9 8 (^76) 5 4 3 (^22 ) 2 1 2 3 2 2 6 2 7 1 1 1 2 1 3 (^11 ) 1 7 1 8 1 9 2 8 2 0 2 2 1 A 0 A 1 A 2 A 3 A 4 A A (^56) A 7 A 8 A 9 A 1 0 A A (^11 ) A 1 3 A 1 4 O 0 O 1 O 2 O 3 O 4 O O (^56) O 7 V C C C E O E V P P

R D

A 1 5 U 4 7 4 H C T 1 3 8 (^12) 3 (^11 ) 1 3 1 2 1 1 1 0 (^97) 6 4 5 A B C Y 0 Y 1 Y 2 Y Y (^34) Y 5 Y 6 Y 7 G 1 G 2 A G 2 B U 2 A T 2 7 2 5 6 1 0 9 8 (^76) 5 4 3 (^22 ) 2 1 2 3 2 2 6 2 7 1 1 1 2 1 3 (^11 ) 1 7 1 8 1 9 2 8 2 0 2 2 1 A 0 A 1 A 2 A 3 A 4 A A (^56) A 7 A 8 A 9 A 1 0 A A (^11 ) A 1 3 A 1 4 O 0 O 1 O 2 O 3 O 4 O O (^56) O 7 V C C C E O E A 1 6^ V^ P^ P A 1 7 A 1 8 U 1 A T 2 7 2 5 6 1 0 9 8 (^76) 5 4 3 (^22 ) 2 1 2 3 2 2 6 2 7 1 1 1 2 1 3 (^11 ) 1 7 1 8 1 9 2 8 2 0 2 2 1 A 0 A 1 A 2 A 3 A 4 A A (^56) A 7 A 8 A 9 A 1 0 A A (^11 ) A 1 3 A 1 4 O 0 O 1 O 2 O 3 O 4 O O (^56) O 7 V C C C E O E V P P A 1 9 I O / # M D 0 - - D 7 V C C

1. Single bit error flag
2. The main differences are the data bus size and the I/O, memory control signal.
3. Bank low enable has replaced the A0 pin.
4. Upper memory bank
5. It does not matter if 16-bit or 8-bit are read because the microprocessor just ignores any data bus bits that are not needed.

A 2 0

B H E

D 0 - D 7 A 2 1 A 1 - A 1 5

W R

H M 6 2 2 5 6 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 1 2 0 2 2 2 7 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 2 8 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E W E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 V C C A 1 7 H M 6 2 2 5 6 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 1 2 0 2 2 2 7 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 2 8 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E W E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 V C C D 8 - D 1 5 H M 6 2 2 5 6 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 1 2 0 2 2 2 7 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 2 8 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E W E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 V C C H M 6 2 2 5 6 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 1 2 0 2 2 2 7 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 2 8 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E W E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 V C C A 1 8 A 2 3 A 0 A 1 6

R D

U 1 8 G A L 2 2 L V 1 0 C / L C C 2 3 4 5 6 7 1 7 1 8 1 9 2 0 2 3 2 4 2 5 2 6 2 1 2 7 9 1 0 1 1 1 2 1 3 1 6 2 8 I / C L K I I I I I I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I I I I I I V C C V C C A 2 2 A 1 9

1. A cycle that does not read data, it only refreshes a row of memory.
2. 15.625 μs

Chapter Eleven

1. The IN instruction inputs data from an external device into the accumulator and the OUT instruction sends data out to an external device from the accumulator.
2. DX
3. AX
4. The INSW inputs data from the I/O port addressed by DX, as a word, into the extra segment memory location addressed by DI; it then increments DI by 2.
5. The basic input interface is a three-state buffer that is enabled for the IN instruction. When the buffer is enabled data is gated onto the data bus and into the accumulator.
6. Handshaking is the act of synchronizing two systems that operate asynchronously.
7. D8–D

or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or A2 or A1; S1002 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or A or (not A1); S1004 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or (not A2) or A1; S1006 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or (not A2) or (not A1); S1008 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or A or A1; S100A <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or A or (not A1); S100C <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or (not A2) or A1; S100E <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or (not A2) or (not A1); end V1;

library ieee; use ieee.std_logic_1164.all; entity DECODER_23 is port ( BHE, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC; S300D, S300B, S1005, S1007: out STD_LOGIC ); end; architecture V1 of DECODER_23 is begin S300D <= A15 or A14 or (not A13) or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or (not A2) or A1 or BHE; S300B <= A15 or A14 or (not A13) or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or (not A3) or A2 or (not A1) or BHE; S1005 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or (not A2) or A1 or BHE; S1007 <= A15 or A14 or A13 or (not A12) or A11 or A10 or A or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3 or (not A2) or (not A1) or BHE; end V1;

1. D0–D
2. 24

1. A0 and A

library ieee; use ieee.std_logic_1164.all; entity DECODER_31 is port ( BLE, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3: in STD_LOGIC; CS: out STD_LOGIC ); end; architecture V1 of DECODER_31 is begin CS <= A15 or A14 or A13 or A12 or A11 or A10 or (not A9) or (not A8) or (not A7) or A6 or A5 or A4 or A3 or BLE end V1; A 1 0 U 1 8 2 C 5 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 4 3 2 1 4 0 3 9 3 8 3 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 4 1 5 1 6 1 7 1 3 1 2 1 1 1 0 5 3 6 9 8 3 5 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 P C 0 P C 1 P C 2 P C 3 P C 4 P C 5 P C 6 P C 7 R D W R A 0 A 1 R E S E T C S V C C A 1 1 A 3 A 4 D 0 - D 7 U 2 G A L 2 2 V 1 0 / L C C 2 3 4 5 6 7 1 7 1 8 1 9 2 0 2 3 2 4 2 5 2 6 2 1 2 7 9 1 0 1 1 1 2 1 3 1 6 2 8 I / C L K I I I I I I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O I I I I I I V C C C S

W R

A 1 A 2 A 1 2 A 1 4 A 6 A 1 3 A 5 A 8 R E S O U T

R D

A 7 A 1 5 A 9

B L E

1. Modes 0, 1, and 2
2. DELAY PROC NEAR