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CS472 1
Chapter 5
The Processor:
Datapath
and Control
CS472 2
Performance
• instruction count
– determined by compiler and instruction set arch.
• clock cycle time
• CPI
We will develop 2 different implementations of the
MIPS instruction set.
• Single cycle
• Multicycle
determined by the implementation
of the processor
CS472 3
Our Implementation
includes a subset of the core MIPS instruction set
• memory reference instructions, lw and sw
• arithmetic-logical instructions, add, sub, and, or, and slt
• branch instructions, beq and j
doesn’t include
• integer multiplication or division
• floating point instructions
CS472 4
Overview
1. Fetch the instruction from memory
2. Decode the instruction. Read 1
or 2 registers using fields of the
instruction. (lw requires just 1 reg.)
3. Address calculation, operation exec,
or branch comparison
4. Memory access
5. Write back
Any
instruction
class
Instruction
class
specific
CS472 7
Digital Logic Review
State
element
Combinational
logic
We can read the contents of a register, send the value through
some combinational logic, and write that register all in the same
clock cycle because we are using edge-triggering.
With edge-triggering, there is no feedback within a single cycle
and the above circuit operates correctly.
CS472 8
Single Cycle Instr. Implementation
• Every instruction begins execution on one clock
edge and completes execution on the next clock
edge.
• All logic is combinational.
• Control circuitry is relatively simple.
• CPI is 1.0 by definition, but clock period is high.
• Load instr. takes the longest. It determines the
clock period.
• Wastes chip area, (need multiple ALU’s ... )
CS472 9
Register File
built using D flip-flops
M u x
Register 0 Register 1
Register n – 1
Register n
M u x
Read data 1
Read data 2
Read register number 1
Read register number 2
Read register number 1 Read data 1
Read data 2
Read register number 2 Register file Write register
Write data Write
CS472 10
Functional Units
PC
Instruction memory
Instruction address
Instruction
a. Instruction memory b. Program counter
Add Sum
c. Adder
ALU control
RegWrite
Registers Write register
Read data 1
Read data 2
Read register 1
Read register 2
Write data
ALU result
ALU
Data
Data
Register numbers
a. Registers b. ALU
Zero
5
5
(^5 )
16 32 Sign extend
b. Sign-extension unit
MemRead
MemWrite
Data memory
Write data
Read data
a. Data memory unit
Address
CS472 13
R-Type Instruction
1. Fetch from instruction memory and increment PC.
2. Read the 2 source registers from the register file.
Main Control unit decodes the op code to determine the
control line settings.
3. The ALU operates on the data.
4. Result is written into a register.
PC is also updated at the end of this step.
CS472 14
add Instruction
add $1, $2, $
R-format
Trace its datapath.
Which functional units are used for this
instruction?
[31-26] [25-21] [20-16] [15-11] [10-6] [5-0]
CS472 15
lw Instruction
lw $1, 100($2)
I-format
Trace its datapath.
How is sw different?
[31-26] [25-21] [20-16] [15-0]
CS472 16
beq Instruction
beq $1, $2, 100
I-format
Trace its datapath.
[31-26] [25-21] [20-16] [15-0]
