Time Cintrol-Data Communication Network-Lecture Slides, Slides of Data Communication Systems and Computer Networks

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• SS-CARE School of Engineering Spring
  • HDL Based Digital Design CE
    • Lecture

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering „ $time „ A built-in variable that represents simulated time „ a unit less integer „ $display($time, “a=%d”, a); „ Delay-Based Timing Control # „ Delay-based timing control in an expression specifies thetime duration between when the statement isencountered and when it is executed „ # statement „ statement is not executed until time unitshave passed „ control is released so that other processes can execute „ used in test code „ used to model propagation delay in combinational logic

# Time Control

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Event-Based Timing Control @

„ @(expression) „ @(expression or expression or …) „ @(posedge onebit) „ @(negedge onebit) „ do not execute statement until event occurs „ @(clk) is same as @(posedge clk or negedge clk) @(clock) q = d; //q = d is executed whenever signal clock changes value @(posedge clock) q = d; //q = d is executed whenever signal clock does a positive transition @(negedge clock) q = d; //q = d is executed whenever signal clock does a negative transition q = @(posedge clock) d; //d is evaluated immediately and assigned to q at the positive edge of clock

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Examples: Timing Control^ „

Delay # „ Event Control @ „ Delay execution until event occurs

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Event OR Control (Sensitivity List) „

//A level-sensitive latch with asynchronous reset always @( reset or clock or d) //Wait for reset or clock or d to change begin if (reset) //if reset signal is high, set q to 0. q = 1'b0; else if(clock) //if clock is high, latch input q = d; end

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Sensitivity List with Comma Operator

„ //A level-sensitive latch with asynchronous reset always @( reset, clock, d) //Wait for reset or clock or d to change begin if (reset) //if reset signal is high, set q to 0. q = 1'b0; else if(clock) //if clock is high, latch input q = d; end

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering „ We must reset all the feedbackregisters in the design. „ Example: reset (active low) the systemafter 5 time units: initial begin rst_n = 1’b1; # 5 rst_n = 1’b0; end

Generating RESET^ Generating RESET