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• SS-CARE School of Engineering Spring
  • HDL Based Digital Design CE
    • Lecture

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Task is called only from initial and alwaysblocks and other tasks in that module

Task contains any behavioral statements,including time control

Order of input, output, and inout definitionsdetermines binding of arguments

input argument may not be reg „ output arguments must be reg task^ task

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Tasks

Syntax „ task_declaration ::= task task_identifier {task_item_declaration} statement or null endtask

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Task Example task leading_1; input [7:0] data_word; output [2:0] position; reg [7:0] temp; reg [2:0] position; begin temp = data_word; position = 3'b111; while (!temp[7]) begin temp = temp << 1; position = position - 1; end end endtask

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Functions „ Syntax:

function_declaration ::= function [range or type] function_identifier; function_call ::= function_identifier (expression {.. , expression})

Example: „

position = leading_1(data_val);

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Function Example function [2:0] leading_1; input [7:0] data_word; reg [7:0] temp; begin temp = data_word; leading_1 = 3'b111; while (!temp[7]) begin temp = temp << 1; leading_1 = leading_1 - 1; end end endfunction

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Time Scales „ Define a time scale for the module dummy //Reference time unit is 100 nanoseconds and precision is 1 ns

`timescale 100 ns / 1 ns module dummy1; reg toggle; //initialize toggle initial toggle = 1'b0; //Flip the toggle register every 5 time units. In this

module 5 time units = 500 ns =.

s

always #5 begin toggle = ~toggle; $display("%d , In %m toggle = %b ", $time, toggle); end endmodule

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Programming Language Interface (PLI) „

PLI provides a powerful capability to extend the Veriloglanguage by allowing users to define their own utilities toaccess the internal design representation.

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PLI can be used to define additional system tasks andfunctions. Typical examples are monitoring tasks, stimulustasks, debugging tasks

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PLI can be used to extract design information such ashierarchy, connectivity, fanout, and number of logic elementsof a certain type

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PLI can be used to write special-purpose or customizedoutput display routines

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Routines that provide stimulus to the simulation can bewritten with PLI. The stimulus could be automaticallygenerated or translated from some other form of stimulus

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General Verilog-based application software can be writtenwith PLI routines

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Reusable Coding

Guidelines

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Reusable RTL Coding Guidelines

Readability

Simplicity

Locality

Portability

Reusability

Reconfigurability

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering File Header

Should be included for all source filesContents

author information „ revision history „ purpose description „ available parameters „ reset scheme and clock domain „ critical timing and asynchronous interface „ test structures

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Comments and Formats

Appropriate comments

process (always block), function, „ Comment end statements „

A separate command per line

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Coding in a tabular manner

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Line length restriction

„ a fixed number between 72- „ Indentation „ 2 spaces „ avoid using tabs

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Coding Practices

Little-endian for multi-bit bus „

[31:0] instead [0:31]

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Operand sizes should match

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Expression in condition must be a 1-bit value if(abc != 16’h0) instead of if(abc)

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Use parentheses in complex statements

„ Do not assign signals don t-care values „ avoid don’t-care propagation „ Reset all storage elements

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Coding Practices „ Use function to model combo logic „

Do not repeat the same code

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Use local variables

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Use loop judiciously

„ improve readability „ increase simulation and synthesis compilation time „ use array equivalent whenever possible „

Use labels

„ help debugging Foo u_foo(...);/single Foo u_foo1(...);//multiple Foo u_foo2(...); always@(a or b or c) begin: p_demo … end