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These lecture slides are from pakistani unvieristy. These are helpful in Data Communication Network course. I hope Instructor M. Mohisn Rahmattulah wont mind me making these public. I got it from my friend. Its points are: Testbench, Reusability, Compliance, Tools, Phase, Diagnostic, Development, Strategy, Assertion, Assumption
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HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering
Testbench architecture with considerations to: Reusability / ease of use / portability / verification language Number of Bus Functional Models (BFMs) to emulate separate busses Synchronization methods between BFMs Transactions definition and sequencing methods Transactions driving methods Verification strategies for design and its subblocks Compliance Matrix Tools
HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering
Create scenarios that engineers do notanticipate
Avoid misunderstanding the spec
Ensure that fixing a bug will not introduceanother bugs Be performed on a regular basis
HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering
Is a statement about a design’s intended behavior Is also named as property; used interchangeably Usually does not map to the real HW (notsynthesizable)
To ensure consistency between the designer’sintention and what he created To guard the design assumptions/properties