Understanding MOSFET Amplifiers: Load Line Analysis & One-Supply Bias Circuit, Slides of Electrical Circuit Analysis

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FETs-

(Field Effect Transistors)

Learning Goals

• Understand the Basic Physics of MOSFET

Operation

• Describe the Regions of Operation of a

MOSFET

• Use the Graphical LOAD-LINE method to

analyze the operation of basic MOSFET

Amplifiers

• Determine the Bias-Point (Q-Point) for

MOSFET circuits

Load Line: Common Source Amp

• Using the values given the Schematic
• Now KVL on Right Loop
• Rearranging
  • Of form: y = mx + b
  • Using given values

vGS = 1V sin( [ 1000 ⋅ 2 π] t ) + 4 V

DD D D DS

DD D D DS or V R i v

V R i v = +

− + +

D

DS DD D

D (^) R v V R

i = −^1 +

20 (^ inmA)

1 k

20 V 1 k

1

D DS D

D DS i v i

i v or = − +

Ω

Ω

= −

Load Line: Common Source Amp

• Thus the LoadLine Equation
• Plot this on the FET vi Curve to determine the Operating Point
• Since this is a LINE need only 2-points - Intercepts are easy - Making a T-Table

Ω

Ω

= − 1 k

20 V 1 k

1 iD vDS

vDS i D

0 20 mA

20V 0

Max and Min Opp-Points

• The common source Amp is designed to Operate in the SATURATION Region. Recall the vGS Eqn
• By sin behavior
  • Reading the vi-LL graph find (vDS ,iD ) co-ords - (vDS ,i (^) D ) (^) max = (4V,16mA) - vGS = 5V - (vDS ,i (^) D ) (^) min = (16V,4mA) - vGS = 3V

vGS = 1V sin ( 2000 π t ) + 4 V

1V 4 V 3V ( Pt-B)

1V 4 V 5V Pt-A ,min

,max =− + =

= + = GS

GS v

v

Voltage Swing

• The common source Amp is must stay in Saturation. For this nFET that means max & min vGS values of 5V & Vto given the 1V amplitude of the sin
• From Last Slide We calculated corresponding

Xmax/min values for vDS

• vDS,min = 4V (vGS = 5)
• vDS,max = 16V (vGS = 3)
• Note that the output direction is Opposite the Input direct
• The ckt produces a SATURATED output Voltage Swing of 4V-16V = −12V

LoadLine Gain

• Notice
  • vGS: 4→
    • V (^) DS: 11→15 (∆ = 4)
  • vGS: 4→
    • V (^) DS: 11→4 (∆ = 7)
• This is due to the NONlinear nature of MOSFETS; they are “Square-Law” devices - The i (^) D lines in SAT are not evenly Spaced

Input

Output

LoadLine Gain

• Since the FET is NOT linear, vout is NOT directly proportional to v (^) in , so we can NOT Define a true Gain
• “Small Signal” methods WILL allow us to define a true grain for the AC part of the voltage input - Requires Calculus - To “Linearize” ckt

Input

Output

Saturation Slippery-Slope

• Must also take care that the small-signal input

does NOT push the FET Out of Saturation at

ANY Time.

• The v (^) in -Amplitude and Bias-Pt Selection could
  • Drive the FET out of SAT and into TRIODE Operation
  • Drive the FET into CutOff (vGS < Vto)

One-Supply Bias Circuit

• Usually only ONE supply voltage is available. In this case set VG with a voltage divider
• By Thevenin - Since the Gate on a IGFET draws NO current, we have a simple voltage divider on the Left thru R 1 & R 2. - Thus VG to GND

G V DD

R R

R

V

1 2

2

1 2

1 2

1 || 2

R R

R R R

R R R

G

G

=

=

One-Supply Bias Circuit

• If the Circuit has been properly Biased the FET is in SATURATION
• In Saturation i D is independent of v DS and equals, at the operating , or Q, point - Recall the KVL eqn on the GATE Loop (now Assumed at the “Q” point): - Sub into SAT eqn

↓ i D

( ) 2 i (^) DQ = K vGSQ − V to

S

G GSQ DQ (^) R

V v i

−

( ) 2 GSQ to S

G GSQ K v V R

V v = −

−

One-Supply Bias Circuit

• Solve for vGSQ :
• Or:
• Introduce new Constant:
• Yields quadratic Eqn in v (^) GSQ :
• Now Solve by MATLAB’s MuPAD

( ) 2 GSQ to S

G GSQ K v V R

V v = −

−

( ) 2 V (^) G − vGSQ = RSK vGSQ − V to U = RS K

UvGSQ^2 + ( 1 − 2 UVto ) v (^) GSQ +( UV (^) to^2 − VG ) = 0

One-Supply Bias Circuit

• Discarding the Negative Root find
• Then Find iDQ by subbing vGSQ from above into

the gate KVL Eqn:

U

UV U V V v (^) GSQ to G to 2

2 − 1 + 4 − + 1

S

G GSQ DQ R

V v i

−

One-Supply Bias Circuit

• Solving the last two eqns yields iDQ and v (^) GSQ - Beware that the parabolic i (^) D eqn will produce an extraneous root - Discard the SMALLER root as SAT requires: vGS−Vto ≥ 0 - The KVL eqn on ckt Right-Side - ReArranging - Then with iDQ from before (MuPAD)

S D

D D DS

DD

R i

R i v

V

0 = − +

v (^) DS = VDD − ( RD + RS ) i (^) D

v (^) GS − Vto = ± iD K v^ DSQ = VDD −^ (^ RD + RS ) i^ DQ

iD ↓