UVM: Universal Verification Methodology - A Comprehensive Guide, Cheat Sheet of Electronics

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UVM: Ready, Set, Deploy!

Base Classes in UVM

Tom Fitzpatrick

Verification Methodologist

The Keys to Verification Productivity

 Don’t reinvent the wheel

• Build on what’s there

 Reuse, Reuse, Reuse

• Modularity, Flexibility and Portability

Your VIP &

Verification

Environments

Class Library

Methodology

UVM Key Concepts

 Test/Testbench Separation

• Improves reusability
• Test customizes testbench

 Phased build process

 Configurability

• Controlled by test
• Structural, run-time parameters
• Allows greater topological flexibility

 TLM Communication

• Improves component modularity
• Enables plug-n-play reuse

 Hierarchical Sequential Stimulus

• Simplified Test Writer interface
• Decouple stimulus from

component hierarchy

Test

Env(Testbench)

VC

Component

Component

VC VC VC

• What does it do?
• What are the use cases?
• Which test cases are required?
• What type of stimulus scenarios are required?
• What represents correct behavior?
• What kind of functional coverage do I need?

For the Design:

UVM Testbench - Architectural

Design

DUT

SPI I/F

APB

IRQ

• How does the interface work?
• What information is transferred?
• Transaction variants?
• Uni/bidirectional? Pipelined?

For Each Interface:

UVC Structural Building Block

DUT

One per

interface

UVC(agent)

Sequencer

Driver

Monitor

Configuration

Object

Stimulus Converts seq_item

to pin wiggles

Sends stimulus

to Driver

Detects transactions

on the interface

Analysis port: Send

transactions for checking

• Contains virtual

interface handle

• Pass information

on how agent

should behave

seq_item

10

class dut_agent extends uvm_component; `uvm_component_utils(dut_agent) dut_agent_cfg m_cfg; uvm_analysis_port #(dut_txn) ap; dut_monitor m_monitor; dut_driver m_driver; uvm_sequencer #(dut_txn) m_seqr; … function void build_phase(uvm_phase phase); … endfunction

function void connect_phase(uvm_phase phase); m_monitor.dut_if = m_cfg.bus_if; ap = m_monitor.ap; if(m_cfg.active == UVM_ACTIVE) begin m_driver.seq_item_port.connect( m_seqr.seq_item_export); m_driver.dut_if = m_cfg.bus_if; end … endfunction

endclass

The Agent

DUT

UVC (agent)

Sequencer Driver

Monitor

Configuration Object

class my_env extends uvm_env; uvm_component_utils(my_env) agent1 m_agent1; agent2 m_agent2; my_scoreboard m_scoreboard; my_env_config m_cfg; function new(string name = “my_env”, uvm_component parent = null); super.new(name, parent); endfunction **function void build_phase(uvm_phase phase);** if(!uvm_config_db #( my_env_config )::get( this , "", “my_env_config" , m_cfg ) beginuvm_error(“Env: build", “can’t get env_config") end if(m_cfg.has_agent1) begin uvm_config_db #(agent1_config)::set( this , "m_agent1","agent1_config",m_cfg.m_agent1_cfg); m_agent1 = agent1::type_id::create("m_agent1", this); end if(m_cfg.has_agent2) begin uvm_config_db #(agent2_config)::set( this , "m_agent2","agent2_config",m_cfg.m_agent2_cfg); m_agent2 = agent2::type_id::create("m_agent2", this); end if(m_cfg.has_my_scoreboard) begin m_scoreboard = my_scoreboard::type_id::create("m_scoreboard", this); end endfunction:build_phase

The Environment

DUT

UVM Configuration Database

 uvm_config_db is a convenience layer

• Explicitly typed
• Tied to hierarchical scopes

test

set e.a.d.x = 4

env

set a.d.x = 3

agent

set d.x = 2;

driver

get x = 4

Path Value

{test .e.a.d.x} 4

{test.e .a.d.x} 3

{test.e.a .d.x} 2

{test.e.a.d .x} 1

Highest Write Wins

test

set e.y = 4

env

get y; set a.y = y

agent

get y; set d.y = y;

driver

get y = (^4)

Usually, a component will get its configuration and use that to configure its children

123

Separating Stimulus from the

Testbench

 A key to reusability is to separate Behavior from Structure

DUT

Behavior

Structure

16

This is the “transaction”

Designing a Sequence Item

class bus_item extends uvm_sequence_item;

`uvm_object_utils(bus_item)

rand int delay;

rand logic[31:0] addr;

rand op_code_enum op_code;

rand logic[31:0] data[];

string slave_name;

bit response;

function new(string name = "bus_item");

super.new(name);

endfunction

endclass: bus_item

Make all “input” properties rand

do_copy() do_compare() convert2string() do_print() do_record() do_pack() do_unpack()

Methods for standard operation

Users call copy(), compare()…

Designing a Sequence Item

class bus_item extends uvm_sequence_item;

`uvm_object_utils(bus_item)

function void do_copy (uvm_object rhs);

bus_item rhs_;

endfunction: do_copy

endclass: bus_item

Virtual method

do_copy() do_compare() convert2string() do_print() do_record() do_pack() do_unpack()

do_copy()

Designing a Sequence Item

class bus_item extends uvm_sequence_item;

`uvm_object_utils(bus_item)

function void do_copy (uvm_object rhs);

bus_item rhs_;

if(!$cast(rhs_, rhs)) begin

uvm_report_error("do_copy:", "Cast failed");

return;

end

super.do_copy(rhs);

endfunction: do_copy

endclass: bus_item

Chain the copy with parent classes

do_copy()

Designing a Sequence Item

class bus_item extends uvm_sequence_item;

`uvm_object_utils(bus_item)

function void do_copy (uvm_object rhs);

bus_item rhs_;

if(!$cast(rhs_, rhs)) begin

uvm_report_error("do_copy:", "Cast failed");

return;

end

super.do_copy(rhs);

delay = rhs_.delay;

addr = rhs_.addr;

op_code = rhs_.op_code;

slave_name = rhs_.slave_name;

data = rhs_.data;

response = rhs_.response;

endfunction: do_copy

endclass: bus_item

Copy members of rhs to this

do_copy()