Verilog Tutorial - Lecture Slides | CS 0447, Exams of Computer Science

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Verilog

Tutorial

25-Oct-

Deepak Kumar Tala

Comments :[email protected]

Website : http://www.deeps.org

Index

Introduction.

History of Verilog.

Design and Tool Flow.

My First Program in Verilog.

Verilog HDL Syntax and Semantics.

Verilog Gate Level Modeling Tutorial.

Verilog Operators.

Verilog behavioral modeling.

Procedural Timing Controls.

Tasks and Function.

System Tasks and Functions.

Art of writing test benches.

Verilog Tutorial on Modeling Memories and FSM.

Parameterized Modules.

Verilog Synthesis Tutorial.

Verilog PLI Tutorial? : 20% Complete

What's new in Verilog 2001? : 50% Complete

Verilog Quick Reference.

Verilog in One Day : This tutorial is in bit lighter sense, with humor, So take it cool and enjoy.

Section for more details) With increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity.

Top-Down Design

The desired design-style of all designers is the top-down design. A real top- down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are mix of both the methods, implementing some key elements of both design styles.

Figure shows a Top-Down design approach.

Abstraction Levels of Verilog

Verilog supports a design at many different levels of abstraction. Three of them are very important:

? Behavioral level ? Register-Transfer Level ? Gate Level

Behavioral level

This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design.

Register-Transfer Level

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times. Modern definition of a RTL code is "Any code that is synthesizable is called RTL code".

Gate Level

Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (0',1', X',Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.

most successful of these was VCS, the Verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed to an interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but simulation execution speed was much faster.

In the meantime, the popularity of Verilog and PLI was rising exponentially. Verilog as a HDL found more admirers than well-formed and federally funded VHDL. It was only a matter of time before people in OVI realized the need of a more universally accepted standard. Accordingly, the board of directors of OVI requested IEEE to form a working committee for establishing Verilog as an IEEE standard. The working committee 1364 was formed in mid 1993 and on October 14, 1993, it had its first meeting.

The standard, which combined both the Verilog language syntax and the PLI in a single volume, was passed in May 1995 and now known as IEEE Std. 1364-

After many years, new features have been added to Verilog, and new version is called Verilog 2001. This version seems to have fixed lot of problems that Verilog 1995 had. This version is called 1364-2000. Only waiting now is that all the tool vendors implementing it.

DESIGN AND TOOL FLOW

Introduction Being new to Verilog you might want to try some examples and try designing something new. I have listed the tool flow that could be used to achieve this. I have personally tried this flow and found this to be working just fine for me. Here I have taken only front end design part of the tool flow and bit of FPGA design flow that can be done without any fat money spent on tools. If you have any suggestions or questions please don't hesitate to mail me. ( Note : I have missed steps in P&R, Will add then shortly)

Various stages of ASIC/FPGA ? Specification : Word processor like Word, Kwriter, AbiWord ? High Level Design : Word processor like Word, Kwriter, AbiWord, for drawing waveform use tools like waveformer or testbencher or Word. ? Micro Design/Low level design: Word processor like Word, Kwriter, AbiWord, for drawing waveform use tools like waveformer or testbencher or Word. For FSM StateCAD or some similar tool. ? RTL Coding : Vim, Emacs, conTEXT, HDL TurboWriter ? Simulation : Modelsim, VCS, Verilog-XL, Veriwell, Finsim, iVerilog, VeriDOS. ? Synthesis : Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. You can download this from FPGA vendors like Altera and Xilinx for free. ? Place & Route : For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic.

Figure : Typical Design flow

Figure : I8155 High Level Block Diagram

Micro Design/Low level design

Low level design or Micro design is the phase in which, designer describes how each block is implemented. It contains details of State machines, counters, Mux, decoders, internal registers. For state machine entry you can use either Word, or special tools like StateCAD. It is always a good idea if waveform is drawn at various interfaces.

Figure : Sample Low level design

RTL Coding

In RTL coding, Micro Design is converted into Verilog/VHDL code, using synthesizable constructs of the language. Normally we use vim editor, but I prefer conTEXT and Nedit editor, it all depends on which editor you like. Some use Emacs.

Figure : Sample RTL code

Simulation

Simulation is the process of verifying the functional characteristics of models at any level of abstraction. We use simulators to simulate the the Hardware models. To test if the RTL code meets the functional requirements of the specification, see if all the RTL blocks are functionally correct. To achieve this we need to write testbench, which generates clk, reset and required test vectors. A sample testbench for a counter is as shown below.

Figure : Synthesis Flow

Figure : Synthesis output

Place & Route

Figure : Sample micro-processor placement

Figure : J-K Flip-Flop

Note : Under construction, please feel free to send your comments

This is a free version of the VeriWell for Win32 Simulator Distribute this freely; call 1-800-VERIWELL for ordering information See the file "!readme.1st" for more information

Copyright (c) 1993-97 Wellspring Solutions, Inc. All rights reserved

Memory Available: 0 Entering Phase I... Compiling source file : hello_world.v The size of this model is [0%, 1%] of the capacity of the free version

Entering Phase II... Entering Phase III... No errors in compilation Top-level modules: hello_world

Hello World by Deepak Exiting VeriWell for Win32 at time 10 0 Errors, 0 Warnings, Memory Used: 0 Compile time = 0.0, Load time = 0.0, Simulation time = 0.

Normal exit

Counter Design Block

Counter Design Specs

? 4-bit synchronous up counter. ? active high, synchronous reset. ? Active high enable.

Counter Design

// This is my second Verilog Design // Design Name : counter // File Name : counter.v // Function : This is a 4 bit up-counter with // Synchronous active high reset and // with active high enable signal //-----------------------------------------------------

module counter ( clock , // Clock input ot the design reset , // active high, synchronous Reset input enable , // Active high enabel signal for counter counter_out // 4 bit vector output of the counter ); // End of port list

//-------------Input Ports----------------------------- input clock ; input reset ; input enable ;

//-------------Output Ports---------------------------- output [3:0] counter_out ;

//-------------Input ports Data Type------------------- // By rule all the input ports should be wires wire clock ; wire reset ; wire enable ;

//-------------Output Ports Data Type------------------ // Output port can be a storage element (reg) or a wire reg [3:0] counter_out ;

//------------Code Starts Here------------------------- // Since this counter is a positive edge trigged one, // We trigger the below block with respect to positive // edge of the clock. always @ (posedge clock) begin : COUNTER // Block Name // At every rising edge of clock we check if reset is active

11 #5 reset = 0; // De-assert the reset 12 #5 enable = 1; // Assert enable 13 #100 enable = 0; // De-assert enable 14 #10 $finish; // Terminate simulation 15end 16// Clock generator 17always begin 18 #5 clock = ~clock; // Toggle clock every 5 ticks 19end 20// Connect DUT to test bench 21counter U_counter ( 22 clock, 23 reset, 24 enable, 25 counter_out 26); 27 28endmodule

Counter Waveform

Note : Simulator used for this exercise can be got from here, If this is illegal, please let me know, I will remove it from my web page.

Verilog HDL Syntax and Semantics

Lexical Conventions The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog HDL is a case-sensitive language. All keywords are in lowercase.

White Space White space can contain the characters for blanks, tabs, newlines, and formfeeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings.

White space characters are :

? Blank spaces ? Tabs ? Carriage returns ? New-line ? Form-feeds

Examples of White Spaces

Functional Equivalent Code module addbit(a,b,ci,sum,co); input a,b,ci;output sum co; wire a,b,ci,sum,co;

module addbit ( a, b, ci, sum, co); input a; input b; input ci; output sum; output co; wire a; wire b; wire ci; wire sum; wire co; Never write code like this. Nice way to write code.