Virtual Memory Systems, Lecture Slide - Computer Science, Slides of Computer System Design and Architecture

Simple Memory System , Core i7/Linux Memory system, Memory Mapping

Typology: Slides

2010/2011

Uploaded on 10/08/2011

rolla45
rolla45 🇺🇸

4

(6)

133 documents

1 / 33

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Carnegie Mellon
1
Virtual(Memory:(Systems(
15#213:'Introduc0on'to'Computer'Systems ''
16th'Lecture,'Oct.'19,'2010'
Instructors:''
Randy'Bryant'and'Dave'O’Hallaron'
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f
pf20
pf21

Partial preview of the text

Download Virtual Memory Systems, Lecture Slide - Computer Science and more Slides Computer System Design and Architecture in PDF only on Docsity!

Virtual Memory: Systems

15-­‐213: Introduc0on to Computer Systems

th

Lecture, Oct. 19, 2010

Instructors:

Randy Bryant and Dave O’Hallaron

Today

 Simple memory system example

 Case study: Core i7/Linux memory system

 Memory mapping

Simple Memory System Example

 Addressing

 14-­‐bit virtual addresses

 12-­‐bit physical address

 Page size = 64 bytes

VPO

PPN PPO

VPN

Virtual Page Number Virtual Page Offset

Physical Page Number Physical Page Offset

Simple Memory System Page Table

Only show first 16 entries (out of 256)

0F 0D 1

0E 11 1

0D 2D 1

0C – 0

0B – 0

0A 09 1

VPN PPN Valid

VPN PPN Valid

Simple Memory System Cache

 16 lines, 4-­‐byte block size

 Physically addressed

 Direct mapped

PPN PPO

CT CI CO

7 16 1 11 C2 DF 03
5 0D 1 36 72 F0 1D
4 32 1 43 6D 8F 09
2 1B 1 00 02 04 08

Idx Tag Valid B0 B1 B2 B F 14 0 – – – –

E 13 1 83 77 1B D
D 16 1 04 96 34 15
C 12 0 – – – –
B 0B 0 – – – –
A 2D 1 93 15 DA 3B
9 2D 0 – – – –
8 24 1 3A 00 51 89

Idx Tag Valid B0 B1 B2 B

Address TranslaZon Example

Virtual Address: 0x03D

VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____

Physical Address

CO ___ CI___ CT ____ Hit? __ Byte: ____

VPN VPO

TLBT TLBI

PPN PPO

CT CI CO

0x0F 0x3 0x03 Y N 0x0D

0 0x5 0x0D Y 0x

Address TranslaZon Example

Virtual Address: 0x

VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____

Physical Address

CO___ CI___ CT ____ Hit? __ Byte: ____

VPN VPO

TLBT TLBI

PPN PPO

CT CI CO

0x00 0 0x00 N N 0x

0 0x8 0x28 N Mem

Today

 Simple memory system example

 Case study: Core i7/Linux memory system

 Memory mapping

Review of Symbols

 Basic Parameters

 N = 2

n

: Number of addresses in virtual address space

 M = 2m^ : Number of addresses in physical address space

 P = 2p^ : Page size (bytes)

 Components of the virtual address (VA)

 TLBI: TLB index

 TLBT: TLB tag

 VPO: Virtual page offset

 VPN: Virtual page number

 Components of the physical address (PA)

 PPO: Physical page offset (same as VPO)

 PPN: Physical page number

 CO: Byte offset within cache line

 CI: Cache index

 CT: Cache tag

End-­‐to-­‐end Core i7 Address TranslaZon

CPU

VPN VPO

36 12

TLBT TLBI

32 4

L1 TLB (16 sets, 4 entries/set)

VPN1 VPN

9 9 PTE

CR

PPN PPO

40 12

Page tables

TLB

miss

TLB

hit

Physical

address

(PA)

Result

32/

CT CO

40 6

CI

6

L2, L3, and

main memory

L1 d-­‐cache

(64 sets, 8 lines/set)

L

hit

L

miss

Virtual address (VA)

VPN3 VPN

9 9 PTE PTE PTE

Core i7 Level 4 Page Table Entries

Page physical base address Unused G (^) D A CD WT U/S R/W P=

Each entry references a 4K child page

P: Child page is present in memory (1) or not (0)

R/W: Read-­‐only or read-­‐write access permission for child page

U/S: User or supervisor mode access

WT: Write-­‐through or write-­‐back cache policy for this page

CD: Cache disabled (1) or enabled (0)

A: Reference bit (set by MMU on reads and writes, cleared by so`ware)

D: Dirty bit (set by MMU on writes, cleared by so`ware)

G: Global page (don’t evict from TLB on task switch)

Page physical base address: 40 most significant bits of physical page address

(forces pages to be 4KB aligned)

XD Unused Available for OS (page locaZon on disk) P=

Core i7 Page Table TranslaZon

CR

Physical address of page Physical address of L1 PT 9 VPO

9 12 Virtual

address

L4 PT

Page table L4 PTE PPN PPO 40 12

Physical

address

Offset into physical and virtual page

VPN 1 VPN 2 VPN 3 VPN 4
L3 PT

Page middle directory L3 PTE

L2 PT

Page upper directory L2 PTE

L1 PT

Page global directory L1 PTE 9 9 40 / 40 / 40 / 40 / 40 / / 12 512 GB region per entry

1 GB

region per entry

2 MB

region per entry

4 KB

region per entry

19

Virtual Memory of a Linux Process

Kernel code and data

Memory mapped region

for shared libraries

RunZme heap (malloc)

Program text (.text)

IniZalized data (.data)

UniniZalized data (.bss)

User stack

% esp

Process

virtual

memory

brk

Physical memory

IdenJcal for

each process

Process-­‐specific data

structs (ptables,

task and mm structs,

kernel stack)

Kernel

virtual

memory

0x08048000 (32) 0x00400000 (64)

Different for

each process

20

vm_next

vm_next

Linux Organizes VM as CollecZon of “Areas”

task_struct

mm_struct

mm pgd

mmap

vm_area_struct

vm_end

vm_prot

vm_start

vm_end

vm_prot

vm_start

vm_end

vm_prot

vm_next

vm_start

Process virtual memory

Text

Data

Shared libraries

 pgd:

 Page global directory address  Points to L1 page table

 vm_prot:

 Read/write permissions for

this area

 vm_flags

 Pages shared with other

processes or private to this

process

vm_flags

vm_flags

vm_flags