FIG.
1o-A
DfACONVERTER can be used to provide the voltage ramp needed to ope rate a
single-counter AID converter.
counter
and
resets
the
counter
for
the
next
conversion.
The
single
-ramp
circuit
is little
more
than
a
controlled
counter
with
avoltage-feedbackloop. 'T he
circuit
is
timed
in
such
a
way
that
when
the
reference
-ramp
voltage
equals
the
applied
input
voltage,
the
binary
count
exist
-
ing
on
the
counter
at
that
mo-
ment
is
the
digitized
value
of
the
analog
signal.
Note
that
the
speed
of
the
clock
and
the
rate
of
the
voltage
ramp
must
both
be
set
correctly
for
the
counter
to
function
properly,
The
time
required
to
perform
a
conversion
will
depend
upon
the
level of
the
analog
input.
Since
the
counter
and
reference
ramp
both
start
from
zero
at
each
con
-
version,
it
will
take
longer
to
match
a
higher
level of
analog
in-
put
than
a
low
level.
The
se
-
quence
of
operations
can
take
place
very
quickly
The
reference-
ramp
voltage
can
change
faster
than
1volt
per
ms
to
reach
the
input
voltage. For
example,
if
an
input
of 2 volts is
applied
to
the
c
ircuit
in
Fig. 8, it
would
take
2 x 1 volt/rns,
which
equals
2
ms
for
the
ramp
voltage to
equal
the
input.
The
actual
binary
count
after
2
ms
depends
on
the
speed
of
the
clock. A
faster
clock
speed
will yield a
higher
count,
and
vice
versa.
Since
the
clock
can
operate
in
-
dependent
of
the
voltage
ramp,
BINARY
OUTPUT
Dual-slope
ADC
The
dual-slope
conversion
technique
offers
the
advantage
of
conversion
stability
at
the
ex-
pense
of
conversion
speed.
The
reference
-ramp
generator
circuit
eliminates
the
effects of
compo
-
nent
drift
over
time
(Fig. 9).
The
inpu
t
signal
of a
dua
l-slope
converter
is
fed
into
an
inte
-
grator.
When
a
positive
input
sig-
nal
is
applied,
the
integrator's
output
voltage
ramps
in
the
negative
direction.
The
negat
ive
voltage forces
the
output
of
the
E
comparator
high.
That
in
turn
!:(
activates
the
clock
input
to
the
(0
counter
which
will
begin
to incre-
(0
unique
opportunities
for
other
outputs
besides
straight
b
inary
become
available.
Some
customized
instrument
Ie's
use
single-slope
techniques
to
con
-
vert
an
analog
input
directly to
binary
coded
decimal
(BCD) to
drive
7-segment
displays.
Th a t
type of flextbtlity is a
strong
ad
-
vantage,
The
pr
imary
d
isadvan
-
tage
of
using
single-slope
tech-
niques
is
the
tendency
toward
unstable
operation
over
time
.
Wi
thout
some
form
of
syn-
chronization
between
the
clock
and
ramp
generator,
any
dri
ft
in
clock
speed
or
ramp
voltage
per
-
formance
will
cause
errors
in
the
output
word.
That's
why
single-
slope
converters
are
not
used
in
high
precision
applications.
.-+-t-i-+--------1
BINA
RY
(
.-+-t-t----;
LATCH )
DfAC
ON
VERT
ER
BIN
ARY
CO
UN
T
ER
TIMING
AND
CONTROL
CI
RC
U
ITS
REFEHEN
CE
VOLTAGE
v
Single-slope
ADC
A
more
efficient
method
of
AID
conversion
is
the
single
-slope AI
0,
also
known
as
the
single
-ramp
AID
(Fig. 8). In
the
single-slope
circuit,
the
cycle
begins
with
the
counter
reset
and
the
ramp
volt-
age
at
zero.
The
comparator's
output
at
that
point
is low, so
no
clock
signals
are
allowed to
reach
the
counter
.
When
an
input
volt-
age is
applied
to
the
converter,
the
comparator's
noninverting
input
(+)
will
exceed
the
voltage
at
the
inverting
(- )
input,
so it's
output
will be
high,
That
will
en
-
able
the
AND
gate,
which
will allow
clock
pulses
to
reach
the
binary
counter.
At
the
same
time,
a
tim
-
ing
circuit
drives
the
voltage
ramp
up,
which
q u ic k
ly
in-
creases
the
reference
voltage
on
the
comparator's
inverting
in
-
put.
When
the
reference
-ramp
voltage
just
exceeds
the
input
voltage,
the
comparator's
output
falls low
again
.
The
clock
pulses
stop
and
the
timing
circuit
latches
the
count
at
the
binary
voltage
set
by
the
voltage-divider
network.
A
network
of
digital
gates
is
used
to
convert
the
array
of
comparator
signals
into
a
bin
-
aryword
which
ismade
available
at
the
converter's
output
.
Our
example
in
Fig. 7
provides
only
two
bits
of
resolution.
A 2-
bit
ADC is
not
very
practical
for
most
applications,
but
it
demon
-
strates
the
key
concepts
needed
to
build
a
flash
converter. As
you
may
have
noticed
from
the
cir-
cu
it
in
Fig. 7, it
takes
2n-1com-
parators
to
support
the
reso
lu-
tion
of
the
converter.
Our
2-bit
ADC
example
requires
22-1, or 3
comparators;
a
4-bit
converter
needs
24-1, or 15
comparators;
an
8
-bit
flash
ADC
needs
28-1,
or
255
comparators,
and
so on.
This
vastly
increasing
complexity
is a
great
disadvantage
in
flash
devices
-not
only
in
the
need
for
additional
comparators,
but
also
in
the
unwieldy
gating
circuitry
as
well.
The
main
advantage
to
flash
converters,
of
course,
is
simple
speed.
Since
the
analog
input
is
applied
to every
comparator
si-
multaneously,
the
conversion
time
is merely
equal
to
the
propa
-
gation
delay of
the
comparators
and
gating
circuitry. A
flash
con-
version
can
be
accomplished
in
just
a few
microseconds.
63