Manejo de Excepciones y Interrupciones en Microcontroladores, Apuntes de Microprocesadores

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Exceptions and Interrupts

Julio Enrique Fajardo

Overview

▪ Exception and Interrupt Concepts

▪ Entering an Exception Handler

▪ Exiting an Exception Handler

▪ Core Interrupts

▪ Using Port Module and External Interrupts

▪ Timing Analysis

▪ Program Design with Interrupts

▪ Sharing Data Safely Between ISRs and Other Threads

Example System with Interrupt

▪ Goal: Change color of RGB LED when switch is pressed

▪ Will explain details of interfacing with switch and LEDs in GPIO module later

▪ Need to add external switch

How to Detect Switch is Pressed?

▪ Polling - use software to check it

▪ Slow - need to explicitly check to see if switch is pressed

▪ Wasteful of CPU time - the faster a response we need, the more often we need to check

▪ Scales badly - difficult to build system with many activities which can respond quickly.

Response time depends on all other processing.

▪ Interrupt - use special hardware in MCU to detect event,

run specific code (interrupt service routine - ISR) in response

▪ Efficient - code runs only when necessary

▪ Fast - hardware mechanism

▪ Scales well

◦ ISR response time doesn’t depend on most other processing.

◦ Code modules can be developed independently

Interrupts

▪ Hardware-triggered asynchronous software routine

▪ Triggered by hardware signal from peripheral or external device

▪ Asynchronous - can happen anywhere in the program (unless interrupt is disabled)

▪ Software routine - Interrupt service routine runs in response to interrupt

▪ Fundamental mechanism of microcontrollers

▪ Provides efficient event-based processing rather than polling

▪ Provides quick response to events regardless* of program state, complexity,

location

▪ Allows many multithreaded embedded systems to be responsive without an

operating system (specifically task scheduler)

▪ Req1: When Switch SW is pressed, ISR will increment count variable

▪ Req2: Main code will light LEDs according to count value in binary sequence (Blue: 4,

Green: 2, Red: 1)

▪ Req3: Main code will toggle its debug line each time it executes

▪ Req4: ISR will raise its debug line (and lower main’s debug line) whenever it is executing

Example Program Requirements & Design ISR count (^) Main (does initialization, then updates LED based on count) SW RGB LED Global Variable ISR Task

Use Debugger for Detailed Processor View

▪ Can see registers, stack, source code, disassembly (object code) ▪ Note: Compiler may generate code for function entry ▪ Place breakpoint on Handler function declaration line in source code, not at first line of function code

ENTERING AN EXCEPTION HANDLER

1. Finish Current Instruction

▪ Most instructions are short and finish quickly

▪ Some instructions may take many cycles to execute

▪ Load Multiple (LDM), Store Multiple (STM), Push, Pop, MULS (32 cycles for some CPU core implementations)

▪ This will delay interrupt response significantly

▪ If one of these is executing when the interrupt is requested, the processor:

▪ abandons the instruction ▪ responds to the interrupt ▪ executes the ISR ▪ returns from interrupt ▪ restarts the abandoned instruction

2. Push Context onto Current Stack

▪ Two SPs: Main (MSP), process (PSP)

▪ Which is active depends on operating mode, CONTROL register bit 1

▪ Stack grows toward smaller addresses

SP points here before interrupt SP + 0x1C xPSR SP + 0x18 PC Decreasing SP + 0x14 LR memory SP + 0x10 R address SP + 0x0C R SP + 0x08 R SP + 0x04 R SP + 0x00 R0 SP points here upon entering ISR

3. Switch to Handler/Privileged Mode

▪ Handler mode always uses Main SP

Thread Mode. MSP or PSP. Handler Mode MSP Reset Starting Exception Processing Exception Processing Completed

Handler and Privileged Mode Mode changed to Handler. Was already using MSP

4. Load PC With Address Of Exception Handler

▪ The program counter is selected from

the vector table depending on

exception

Memory Address Value 0x0000_0000 Initial Stack Pointer 0x0000_0004 Reset 0x0000_0008 NMI_IRQHandler … IRQ0_Handler IRQ1_Handler … Reset: … NMI_IRQHandler: … IRQ0_Handler: … IRQ1_Handler:

Can Examine Vector Table With Debugger

▪ Why is the vector odd?

▪ LSB of address indicates that

handler uses Thumb code

Exception number IRQ number Vector Offset Initial SP 0x 1 Reset 0x 2 - 14 NMI 0x 3 - 13 HardFault 0x0C 4 Reserved 0x 5 6 7 8 9 10 11 - 5 SVCall 0x2C 12 Reserved 13 14 - 2 PendSV 0x 15 - 1 SysTick 0x3C 16 0 IRQ0 0x 17 1 IRQ1 0x 18 2 IRQ2 0x

.. 16+n n IRQn 0x40+4n