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Microcontroller Instruction Set
For interrupt response time information, refer to the hardware description chapter.
Note: 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or
bits in the PSW) also affect flag settings.
Instructions that Affect Flag Settings
Instruction Flag Instruction Flag
C OV AC C OV AC
ADD X X X CLR C O
ADDC X X X CPL C X
SUBB X X X ANL C,bit X
MUL O X ANL C,/bit X
DIV O X ORL C,bit X
DA X ORL C,/bit X
RRC X MOV C,bit X
RLC X CJNE X
SETB C 1
The Instruction Set and Addressing Modes
Rn Register R7-R0 of the currently selected Register Bank.
direct 8-bit internal data location’s address. This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O port, control register, status register, etc.
(128-255)].
@Ri 8-bit internal data RAM location (0-255) addressed indirectly through register
R1or R0.
#data 8-bit constant included in instruction.
#data 16 16-bit constant included in instruction.
addr 16 16-bit destination address. Used by LCALL and LJMP. A branch can be
anywhere within the 64K byte Program Memory address space.
addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be
within the same 2K byte page of program memory as the first byte of the
following instruction.
rel Signed (two’s complement) 8-bit offset byte. Used by SJMP and all
conditional jumps. Range is -128 to +127 bytes relative to first byte of the
following instruction.
bit Direct Addressed bit in Internal Data RAM or Special Function Register.
0509B-B–12/
Instruction Set
2-72 Instruction Set
Instruction Set Summary
Note: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle
0 NOP JBC
bit,rel [3B, 2C]
JB
bit, rel [3B, 2C]
JNB
bit, rel [3B, 2C]
JC
rel [2B, 2C]
JNC
rel [2B, 2C]
JZ
rel [2B, 2C]
JNZ
rel [2B, 2C]
1 AJMP (P0) [2B, 2C]
ACALL
(P0)
[2B, 2C]
AJMP
(P1)
[2B, 2C]
ACALL
(P1)
[2B, 2C]
AJMP
(P2)
[2B, 2C]
ACALL
(P2)
[2B, 2C]
AJMP
(P3)
[2B, 2C]
ACALL
(P3)
[2B, 2C]
2 LJMP
addr [3B, 2C]
LCALL
addr [3B, 2C]
RET
[2C]
RETI
[2C]
ORL
dir, A [2B]
ANL
dir, A [2B]
XRL
dir, a [2B]
ORL
C, bit [2B, 2C]
3 RR A
RRC
A
RL
A
RLC
A
ORL
dir, #data [3B, 2C]
ANL
dir, #data [3B, 2C]
XRL
dir, #data [3B, 2C]
JMP
@A + DPTR
[2C]
4 INC
A
DEC
A
ADD
A, #data [2B]
ADDC
A, #data [2B]
ORL
A, #data [2B]
ANL
A, #data [2B]
XRL
A, #data [2B]
MOV
A, #data [2B]
5 INC dir [2B]
DEC
dir [2B]
ADD
A, dir [2B]
ADDC
A, dir [2B]
ORL
A, dir [2B]
ANL
A, dir [2B]
XRL
A, dir [2B]
MOV
dir, #data [3B, 2C]
6 INC @R
DEC
@R
ADD
A, @R
ADDC
A, @R
ORL
A, @R
ANL
A, @R
XRL
A, @R
MOV
@R0, @data [2B]
7 INC @R
DEC
@R
ADD
A, @R
ADDC
A, @R
ORL
A, @R
ANL
A, @R
XRL
A, @R
MOV
@R1, #data [2B]
8 INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R0, #data [2B]
9 INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R1, #data [2B]
A INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R2, #data [2B]
B INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R3, #data [2B]
C INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R4, #data [2B]
D INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R5, #data [2B]
E INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R6, #data [2B]
F INC R
DEC
R
ADD
A, R
ADDC
A, R
ORL
A, R
ANL
A, R
XRL
A, R
MOV
R7, #data [2B]
2-74 Instruction Set
Table 1. AT89 Instruction Set Summary(1)
Note: 1. All mnemonics copyrighted © Intel Corp., 1980.
Mnemonic Description Byte Oscillator Period
ARITHMETIC OPERATIONS
ADD A,R (^) n Add register to Accumulator
ADD A,direct Add direct byte to Accumulator
ADD A,@R (^) i Add indirect RAM to Accumulator
ADD A,#data Add immediate data to Accumulator
ADDC A,R (^) n Add register to Accumulator with Carry
ADDC A,direct Add direct byte to Accumulator with Carry
ADDC A,@R (^) i Add indirect RAM to Accumulator with Carry
ADDC A,#data Add immediate data to Acc with Carry
SUBB A,R (^) n Subtract Register from Acc with borrow
SUBB A,direct Subtract direct byte from Acc with borrow
SUBB A,@R (^) i Subtract indirect RAM from ACC with borrow
SUBB A,#data Subtract immediate data from Acc with borrow
INC A Increment Accumulator 1 12
INC R (^) n Increment register 1 12
INC direct Increment direct byte 2 12
INC @R (^) i Increment direct RAM 1 12
DEC A Decrement Accumulator 1 12
DEC R (^) n Decrement Register 1 12
DEC direct Decrement direct byte 2 12
DEC @R (^) i Decrement indirect RAM 1 12
INC DPTR Increment Data Pointer 1 24
MUL AB Multiply A & B 1 48
DIV AB Divide A by B 1 48
DA A Decimal Adjust Accumulator
Mnemonic Description Byte Oscillator Period
LOGICAL OPERATIONS
ANL A,R (^) n AND Register to Accumulator
ANL A,direct AND direct byte to Accumulator
ANL A,@R (^) i AND indirect RAM to Accumulator
ANL A,#data AND immediate data to Accumulator
ANL direct,A AND Accumulator to direct byte
ANL direct,#data AND immediate data to direct byte
ORL A,R (^) n OR register to Accumulator
ORL A,direct OR direct byte to Accumulator
ORL A,@R (^) i OR indirect RAM to Accumulator
ORL A,#data OR immediate data to Accumulator
ORL direct,A OR Accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
XRL A,R (^) n Exclusive-OR register to Accumulator
XRL A,direct Exclusive-OR direct byte to Accumulator
XRL A,@R (^) i Exclusive-OR indirect RAM to Accumulator
XRL A,#data Exclusive-OR immediate data to Accumulator
XRL direct,A Exclusive-OR Accumulator to direct byte
XRL direct,#data Exclusive-OR immediate data to direct byte
CLR A Clear Accumulator 1 12
CPL A Complement Accumulator
RL A Rotate Accumulator Left 1 12
RLC A Rotate Accumulator Left through the Carry
LOGICAL OPERATIONS (continued)
Instruction Set
RR A Rotate Accumulator Right
RRC A Rotate Accumulator Right through the Carry
SWAP A Swap nibbles within the Accumulator
DATA TRANSFER
MOV A,R (^) n Move register to Accumulator
MOV A,direct Move direct byte to Accumulator
MOV A,@R (^) i Move indirect RAM to Accumulator
MOV A,#data Move immediate data to Accumulator
MOV R (^) n ,A Move Accumulator to register
MOV R (^) n ,direct Move direct byte to register
MOV R (^) n ,#data Move immediate data to register
MOV direct,A Move Accumulator to direct byte
MOV direct,R (^) n Move register to direct byte
MOV direct,direct Move direct byte to direct 3 24
MOV direct,@R (^) i Move indirect RAM to direct byte
MOV direct,#data Move immediate data to direct byte
MOV @R (^) i ,A Move Accumulator to indirect RAM
MOV @R (^) i ,direct Move direct byte to indirect RAM
MOV @R (^) i ,#data Move immediate data to indirect RAM
MOV DPTR,#data16 Load Data Pointer with a 16-bit constant
MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc
MOVC A,@A+PC Move Code byte relative to PC to Acc
MOVX A,@R (^) i Move External RAM (8- bit addr) to Acc
DATA TRANSFER (continued)
Mnemonic Description Byte Oscillator Period
MOVX A,@DPTR Move Exernal RAM (16- bit addr) to Acc
MOVX @R (^) i ,A Move Acc to External RAM (8-bit addr)
MOVX @DPTR,A Move Acc to External RAM (16-bit addr)
PUSH direct Push direct byte onto stack
POP direct Pop direct byte from stack
XCH A,R (^) n Exchange register with Accumulator
XCH A,direct Exchange direct byte with Accumulator
XCH A,@R (^) i Exchange indirect RAM with Accumulator
XCHD A,@R (^) i Exchange low-order Digit indirect RAM with Acc
BOOLEAN VARIABLE MANIPULATION
CLR C Clear Carry 1 12
CLR bit Clear direct bit 2 12
SETB C Set Carry 1 12
SETB bit Set direct bit 2 12
CPL C Complement Carry 1 12
CPL bit Complement direct bit 2 12
ANL C,bit AND direct bit to CARRY 2 24
ANL C,/bit AND complement of direct bit to Carry
ORL C,bit OR direct bit to Carry 2 24
ORL C,/bit OR complement of direct bit to Carry
MOV C,bit Move direct bit to Carry 2 12
MOV bit,C Move Carry to direct bit 2 24
JC rel Jump if Carry is set 2 24
JNC rel Jump if Carry not set 2 24
JB bit,rel Jump if direct Bit is set 3 24
JNB bit,rel Jump if direct Bit is Not set
JBC bit,rel Jump if direct Bit is set & clear bit
PROGRAM BRANCHING
Mnemonic Description Byte Oscillator Period
Instruction Set
Table 2. Instruction Opcodes in Hexadecimal Order
Hex Code
Number of Bytes
Mnemonic Operands
00 1 NOP
01 2 AJMP code addr
02 3 LJMP code addr
03 1 RR A
04 1 INC A
05 2 INC data addr
06 1 INC @R
07 1 INC @R
08 1 INC R
09 1 INC R
0A 1 INC R
0B 1 INC R
0C 1 INC R
0D 1 INC R
0E 1 INC R
0F 1 INC R
10 3 JBC bit addr,code addr
11 2 ACALL code addr
12 3 LCALL code addr
13 1 RRC A
14 1 DEC A
15 2 DEC data addr
16 1 DEC @R
17 1 DEC @R
18 1 DEC R
19 1 DEC R
1A 1 DEC R
1B 1 DEC R
1C 1 DEC R
1D 1 DEC R
1E 1 DEC R
1F 1 DEC R
20 3 JB bit addr,code addr
21 2 AJMP code addr
22 1 RET
23 1 RL A
24 2 ADD A,#data
25 2 ADD A,data addr
Hex Code
Number of Bytes
Mnemonic Operands
26 1 ADD A,@R
27 1 ADD A,@R
28 1 ADD A,R
29 1 ADD A,R
2A 1 ADD A,R
2B 1 ADD A,R
2C 1 ADD A,R
2D 1 ADD A,R
2E 1 ADD A,R
2F 1 ADD A,R
30 3 JNB bit addr,code addr
31 2 ACALL code addr
32 1 RETI
33 1 RLC A
34 2 ADDC A,#data
35 2 ADDC A,data addr
36 1 ADDC A,@R
37 1 ADDC A,@R
38 1 ADDC A,R
39 1 ADDC A,R
3A 1 ADDC A,R
3B 1 ADDC A,R
3C 1 ADDC A,R
3D 1 ADDC A,R
3E 1 ADDC A,R
3F 1 ADDC A,R
40 2 JC code addr
41 2 AJMP code addr
42 2 ORL data addr,A
43 3 ORL data addr,#data
44 2 ORL A,#data
45 2 ORL A,data addr
46 1 ORL A,@R
47 1 ORL A,@R
48 1 ORL A,R
49 1 ORL A,R
4A 1 ORL A,R
2-78 Instruction Set
4B 1 ORL A,R
4C 1 ORL A,R
4D 1 ORL A,R
4E 1 ORL A,R
4F 1 ORL A,R
50 2 JNC code addr
51 2 ACALL code addr
52 2 ANL data addr,A
53 3 ANL data addr,#data
54 2 ANL A,#data
55 2 ANL A,data addr
56 1 ANL A,@R
57 1 ANL A,@R
58 1 ANL A,R
59 1 ANL A,R
5A 1 ANL A,R
5B 1 ANL A,R
5C 1 ANL A,R
5D 1 ANL A,R
5E 1 ANL A,R
5F 1 ANL A,R
60 2 JZ code addr
61 2 AJMP code addr
62 2 XRL data addr,A
63 3 XRL data addr,#data
64 2 XRL A,#data
65 2 XRL A,data addr
66 1 XRL A,@R
67 1 XRL A,@R
68 1 XRL A,R
69 1 XRL A,R
6A 1 XRL A,R
6B 1 XRL A,R
6C 1 XRL A,R
6D 1 XRL A,R
6E 1 XRL A,R
6F 1 XRL A,R
70 2 JNZ code addr
Hex Code
Number of Bytes
Mnemonic Operands
71 2 ACALL code addr
72 2 ORL C,bit addr
73 1 JMP @A+DPTR
74 2 MOV A,#data
75 3 MOV data addr,#data
76 2 MOV @R0,#data
77 2 MOV @R1,#data
78 2 MOV R0,#data
79 2 MOV R1,#data
7A 2 MOV R2,#data
7B 2 MOV R3,#data
7C 2 MOV R4,#data
7D 2 MOV R5,#data
7E 2 MOV R6,#data
7F 2 MOV R7,#data
80 2 SJMP code addr
81 2 AJMP code addr
82 2 ANL C,bit addr
83 1 MOVC A,@A+PC
84 1 DIV AB
85 3 MOV data addr,data addr
86 2 MOV data addr,@R
87 2 MOV data addr,@R
88 2 MOV data addr,R
89 2 MOV data addr,R
8A 2 MOV data addr,R
8B 2 MOV data addr,R
8C 2 MOV data addr,R
8D 2 MOV data addr,R
8E 2 MOV data addr,R
8F 2 MOV data addr,R
90 3 MOV DPTR,#data
91 2 ACALL code addr
92 2 MOV bit addr,C
93 1 MOVC A,@A+DPTR
94 2 SUBB A,#data
95 2 SUBB A,data addr
96 1 SUBB A,@R
Hex Code
Number of Bytes
Mnemonic Operands
2-80 Instruction Set
E3 1 MOVX A,@R
E4 1 CLR A
E5 2 MOV A,data addr
E6 1 MOV A,@R
E7 1 MOV A,@R
E8 1 MOV A,R
E9 1 MOV A,R
EA 1 MOV A,R
EB 1 MOV A,R
EC 1 MOV A,R
ED 1 MOV A,R
EE 1 MOV A,R
EF 1 MOV A,R
F0 1 MOVX @DPTR,A
F1 2 ACALL code addr
F2 1 MOVX @R0,A
F3 1 MOVX @R1,A
F4 1 CPL A
F5 2 MOV data addr,A
F6 1 MOV @R0,A
F7 1 MOV @R1,A
F8 1 MOV R0,A
F9 1 MOV R1,A
FA 1 MOV R2,A
FB 1 MOV R3,A
FC 1 MOV R4,A
FD 1 MOV R5,A
FE 1 MOV R6,A
FF 1 MOV R7,A
Hex Code
Number of Bytes
Mnemonic Operands
Instruction Set
Instruction Definitions
ACALL addr
Function: Absolute Call
Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC
twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order
byte first) and increments the Stack Pointer twice. The destination address is obtained by successively
concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the
instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the
first byte of the instruction following ACALL. No flags are affected.
Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following
instruction,
ACALL SUBRTN
at location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively,
and the PC contains 0345H.
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a
Operation: ACALL
(PC) ← (PC) + 2
(SP) ← (SP) + 1
((SP)) ← (PC7-0 )
(SP) ← (SP) + 1
((SP)) ← (PC15-8)
(PC10-0 ) ← page address
Instruction Set
ADDC A, <src-byte>
Function: Add with Carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the
result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7
or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV
is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive
operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The
following instruction,
ADDC A,R
leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.
ADDC A,Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 1 r r r
Operation: ADDC
(A) ← (A) + (C) + (Rn)
ADDC A,direct
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 0 1 direct address
Operation: ADDC
(A) ← (A) + (C) + (direct)
ADDC A,@R i
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 0 1 1 i
Operation: ADDC
(A) ← (A) + (C) + ((Ri))
ADDC A,#data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 0 0 immediate data
Operation: ADDC
(A) ← (A) + (C) + #data
2-84 Instruction Set
AJMP addr
ANL <dest-byte>,<src-byte>
Function: Absolute Jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the
high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of
the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of
the instruction following AJMP.
Example: The label JMPADR is at program memory location 0123H. The following instruction,
AJMP JMPADR
is at location 0345H and loads the PC with 0123H.
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a
Operation: AJMP
(PC) ← (PC) + 2
(PC10-0 ) ← page address
Function: Logical-AND for byte variables
Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the
destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source
can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the
source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original port data will be read
from the output data latch,not the input pins.
Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following
instruction,
ANL A,R
leaves 41H (01000001B) in the Accumulator.
When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM
location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a
constant contained in the instruction or a value computed in the Accumulator at run-time. The following
instruction,
ANL P1,#01110011B
clears bits 7, 3, and 2 of output port 1.
ANL A,R n
Bytes: 1
Cycles: 1
Encoding: 0 1 0 1 1 r r r
Operation: ANL
(A) ← (A) ∧ (Rn )
2-86 Instruction Set
ANL C,<src-bit>
Function: Logical-AND for bit variables
Description: If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction
leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates
that the logical complement of the addressed bit is used as the source value,but the source bit itself is not
affected. No other flags are affected.
Only direct addressing is allowed for the source operand.
Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:
MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN STATE
ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG
ANL C,bit
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 0 0 1 0 bit address
Operation: ANL
(C) ← (C) ∧ (bit)
ANL C,/bit
Bytes: 2
Cycles: 2
Encoding: 1 0 1 1 0 0 0 0 bit address
Operation: ANL
(C) ← (C) ∧ (bit)
Instruction Set
CJNE <dest-byte>,<src-byte>, rel
Function: Compare and Jump if Not Equal.
Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch
destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after
incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of
<dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither
operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be compared with any
directly addressed byte or immediate data, and any indirect RAM location or working register can be compared
with an immediate constant.
Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE R7, # 60H, NOT_EQ
;........ ;R7 = 60H.
NOT_EQ: JC REQ_LOW ;IF R7 < 60H.
;........ ;R7 > 60H.
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction
determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the following instruction,
WAIT: CJNE A, P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the
data read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data
changes to 34H.)
CJNE A,direct,rel
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 0 1 direct address rel. address
Operation: (PC) ← (PC) + 3
IF (A) < > (direct)
THEN
(PC) ← (PC) +relative offset
IF (A) < (direct)
THEN
(C) ← 1
ELSE
(C) ← 0
Instruction Set
CLR A
CLR bit
Function: Clear Accumulator
Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected
Example: The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H
(00000000B).
Bytes: 1
Cycles: 1
Encoding: 1 1 1 0 0 1 0 0
Operation: CLR
(A) ← 0
Function: Clear bit
Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any
directly addressable bit.
Example: Port 1 has previously been written with 5DH (01011101B). The following instruction,CLR P1.2 leaves the port set
to 59H (01011001B).
CLR C
Bytes: 1
Cycles: 1
Encoding: 1 1 0 0 0 0 1 1
Operation: CLR
(C) ← 0
CLR bit
Bytes: 2
Cycles: 1
Encoding: 1 1 0 0 0 0 1 0 bit address
Operation: CLR
(bit) ← 0
2-90 Instruction Set
CPL A
CPL bit
Function: Complement Accumulator
Description: CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a
1 are changed to a 0 and vice-versa. No flags are affected.
Example: The Accumulator contains 5CH (01011100B). The following instruction,
CPL A
leaves the Accumulator set to 0A3H (10100011B).
Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 0 0
Operation: CPL
(A) ← (A)
Function: Complement bit
Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other
flags are affected. CLR can operate on the carry or any directly addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original data is read from the
output data latch,not the input pin.
Example: Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,CPL P1.1CPL
P1.2 leaves the port set to 5BH (01011011B).
CPL C
Bytes: 1
Cycles: 1
Encoding: 1 0 1 1 0 0 1 1
Operation: CPL
(C) ← (C)
CPL bit
Bytes: 2
Cycles: 1
Encoding: 1 0 1 1 0 0 1 0 bit address
Operation: CPL
(bit) ← (bit)
