ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #2
Total: 76pts.
Due 9:30am, Wednesday, January 28, 2009
Consider the 0.25-micron CMOS technology used in the Lab for an inverter with
device sizes as follows: PMOS W=9.0µm, L=1.2µm and NMOS W=2.5µm, L=1.2µm,
respectively, and VDD = 2.5V. Work with the parameters given in Table 3-2 on Page 103
of the Text.
Tasks:
1) Obtain analytically VM, VIL and VIH. Work with the piece-wise linear VTC model
and assume that velocity saturation must be taken into account. (30 pts.)
2) Obtain graphically VM, VIL and VIH but now work with Design Architect to model
this circuit and simulate it using ELDO along with Xelga. Refer to the Mentor Graphics
Tutorial that is posted on the Class Web Page, and Labs One and Two. Turn in a hard
copy of your circuit schematic diagram and commented simulation printouts
showing VM, VIL and VIH, respectively. Compare your simulation results with the
calculated ones in Task 1.
(30 pts.)
3) Obtain graphically the tPLH and tPHL propagation delays. Work with the 50% values of
the input and output signal waveforms as a reference. (16 pts.)