ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
ECE 4500 Project Assignment #2
ECE 5950 Project Assignment #3
(Team Project)
Total: 40 pts. (10% of course grade)
Due 3:00pm, Thursday, April 16, 2009
Demonstrations in the B-214 lab
Specifications:
Design a Dual 4 4-Bit Register Bank (DRB) by using any design style in static
CMOS technology. Each bank of the DRB (Registers R0 - R3, and R4 - R7,
respectively) should include the necessary address decoder, read/write, pre-charge, sense
amplifier, temporary buffer register and three-state buffer circuits. Please refer to Page 3
for the basic architecture, and to the “Hints” (five pages) that are posted under the Design
Clinic Section of the Class Web Page. The DRB is specified such that one bank may be
accessed simultaneously with the other one. Your final design should only have the
following input and output signals:
×
- B0_S, and B1_S active-high Bank Select signals,
- B0_DIN0 - 3, and B1_DIN0 - 3 data input lines,
- B0_A0 - A1, and B1_A0 - A1 address lines, where A1 is most significant,
- B0_R/W*, and B1_R/W* Bank Read/Write* signals (sign * stands for active
low signal),
- B0_LD, and B1_LD signals (active-high) to load temporary registers TMP0 and
TMP1, respectively,
- B0_DEN, and B1_DEN TS buffer enable signals (active-high),
- B0_DOUT0 - 3, and B1_DOUT0 - 3 data output lines,
- VDD and VSS.
The terminal configuration of the layout should allow access to all input signals from the
top, and all output signals from the bottom of the cell. The power lines should be on first-
layer metal rails that pass completely through the cell in a horizontal direction.
Be as generous as you can with the widths of the power lines so that their current-
carrying capabilities will be reasonably high. Use W/L ratios for your transistors such
that the circuit outputs will exhibit near minimum average propagation delays. You are
going to work with a 0.25-micron CMOS technology, however, the minimum feature size
(LMIN) should not be less than 1.2 µm.
Tasks:
1. Give a complete discussion of your design that includes all internal modules and
sizing
of the devices.
