Digital Electronics - Homework Assignment 8 | ECE 4500, Assignments of Digital Electronics

Material Type: Assignment; Professor: Grantner; Class: Digital Electronics; Subject: Electrical & Computer Engineer; University: Western Michigan University; Term: Spring 2009;

Typology: Assignments

Pre 2010

Uploaded on 08/19/2009

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ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #8
Total: 60 pts.
Due 9:30am, Wednesday, March 25, 2009
Consider the CMOS Schmitt Trigger circuit as shown in Fig 7-47on Page 365 of the
Text. Assume the 0.25-micron CMOS technology used in the Lab for the M2-M1
inverter with device sizes as follows: PMOS W=4.0µm, L=1.2µm and NMOS
W=2.0µm, L=1.2µm, respectively.
Tasks:
a) Devise analytically the required sizes for the devices M4 and M3, respectively, such
that VM+ = 1.5V and VM- = 0.9V. (30 pts.)
b) Model your Schmitt Trigger circuit using Design Architect and simulate its behavior
using ELDO and Xelga. Turn in printouts of the circuit diagram and the simulation
results. Compare the simulation results for VM+ and VM-, respectively, with your
analytical results in Part a) and comment on them. No layout is needed. (30 pts.)

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ECE 4500/5950 DIGITAL ELECTRONICS

SPRING 2009

Homework Assignment # Total: 60 pts. Due 9:30am, Wednesday, March 25, 2009

Consider the CMOS Schmitt Trigger circuit as shown in Fig 7-47on Page 365 of the Text. Assume the 0.25-micron CMOS technology used in the Lab for the M 2 -M 1 inverter with device sizes as follows: PMOS W=4.0μm, L=1.2μm and NMOS W=2.0μm, L=1.2μm, respectively.

Tasks:

a) Devise analytically the required sizes for the devices M 4 and M 3 , respectively, such that VM+ = 1.5V and VM- = 0.9V. (30 pts.)

b) Model your Schmitt Trigger circuit using Design Architect and simulate its behavior using ELDO and Xelga. Turn in printouts of the circuit diagram and the simulation results. Compare the simulation results for VM+ and VM-, respectively, with your analytical results in Part a) and comment on them. No layout is needed. (30 pts.)