Homework #3 Solutions
5.4 We have 256 locations in memory and each location is 16-bits.
a) 8 bits are required for the address.
b) 5 bits are needed to allow transfer between instructions 20 locations away
c) The PC-relative offset is 6 (The PC has already been incremented once)
5.9
We could use c, which is a branch that never is taken and goes nowhere. The add
instruction sets condition codes so it actually has some effect on the system.
5.14
(1): 1001 100 001 111111
(2): 1001 101 010 111111
(3): 0101 110 100 000 101
(4): 1001 011 110 111111
5.16
a) PC-Relative addressing will work in this case because the offset is within the range of
numbers that can be stored in the offset field of the instruction.
b) Indirect addressing or Base+Offset addressing will work because we need a register
to hold the address since we can no longer place it in the offset field of the instruction.
c) Base+Offset addressing is the most sensible addressing mode when loading a
sequential array of values.
5.17
LD Instruction: Reads the IR from Memory = 1
Read the data = 1
Total = 2
LDI Instruction: Read the IR from Memory = 1
Read the address to look at from memory = 1
Read the value from memory = 1
Total = 3
LEA Instruction: Read the IR from Memory = 1
Total = 1
5.21
The LC-3 can currently support 256 different trap routines. This is because the low order
8-bits of the TRAP instruction determine which element of the TRAP vector contains the
next address to execute.
5.29
a) LDR R2, R1, #0
STR R2, R0, #0
b) MAR <- SR
