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EECS 373 Final Exam
Fall 2006
Name: ____________________________________ unique name: _____________ Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so.
Scores:
Page/Part # Points
Part 1 /
Part 2 /
Part 3 /
Total /
NOTES:
- Open ABI and White book only
- There are 13 pages total. Count them. We’ve left a lot of room for you to answer questions…
- Calculators are allowed, but no PDAs, Portables, Cell phones, etc.
- Don’t spend too much time on any one problem.
- You have about 120 minutes for the exam.
- Some questions may be more difficult than others. You may want to skip around.
Be sure to show work and explain what you’ve done when asked to do so.
h) A page fault / timer reference interrupt / external IRQ interrupt is a type of synchronous interrupt.
2. Consider a packet consisting of 11 bits. There are 7 data bits (A-G) and 4 parity bits (W-Z) in the packet. So a packet looks as follows: A B C D E F G W X Y Z The intent of the scheme is to be able to correct one bit of error (one bit-flip) in the packet. Let the function P() return a 1 if there are an odd number of 1s provided as arguments, otherwise it is a zero. So P(0,1,0,0) would return a “1”, while P(0,1,1,0) would return a “0”. Say that W, X, and Y are computed as follows: W=P(A, B, C, D, E) X=P(A, B, F) Y=P(A, B, C, D, G) In order to be able to correct any one-bit error (in the data or parity bits) what should the function for “Z” be? (If there is more than one correct answer, you can just provide one of them!) [8] 3. Write the hexadecimal encoding of the following instruction: andis. r3, r31, -4 [5]
- Consider the following circuit. a) Assuming Vref is 4.0V, and there is an absolute error of ±1/4 LSB, what range of input voltages might cause a value of 100 2 to come out of the encoder? Show your work. [4] b) Given the same assumptions as above, what range of input values are certain to cause a value of 100 2 to come out of the encoder? Show your work. [4]
- Consider the following circuit: Assuming there is no error beyond quantization error, indicate what the value of Vout would be given each of the following values of Vin. Vref is 8V. [2 points each] a) Vin=1.2 Volts _____________ b) Vin=2.3 Volts ____________ c) Vin=3.1 Volts _____________
DS500 DATA Register Timing RDR D[7:0] Enable to Data Out (10ns) DS500 SM TIMING SM SM minimum pulse width, 200ns You may assume the following : The sensor bus is mapped to the appropriate PROC MACRO connections. D0 ppc D31, D1 ppcD30… D7 ppc D PD_OUT_EN is implemented All propagation delays are insignificant. MPC823 data setup and hold times are ¼ clock cycle. MPC823 TA* setup and hold times are ¼ clock cycle. MPC823 bus clock is running at 10Mhz. Address is 0x
Part 1a (5 points): Sketch a minimum wait state timing solution for the data register interface.
Part 2a (5 points): Use write cycle to generate the start of measurement signal. How many wait states are required to satisfy the generation of the minimum pulse width for SM?___________
Part 2b (5 points) Provide the logic to generate TA* and SM that will emulate your timing diagram. You may use HDL or schematic form. You need only decode A6 – A11. Draw and label clearly! Part 3a (4 points): To what values should MPC823 device registers should be initialized to provide and enable an edge triggered interrupt on IRQ0? Assume there are no other interrupts. Write the registers in the sequence that you would initialize them and name the bits that should be set. For example, SIPEND, LVL3.
