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Material Type: Exam; Class: Des Microproc Syst; Subject: Electrical Engineering And Computer Science; University: University of Michigan - Ann Arbor; Term: Unknown 2007;
Typology: Exams
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Name: ____________________________________ unique name: _____________
Sign the honor code:
I have neither given nor received aid on this exam nor observed anyone else doing so.
Scores:
a) A 16 Mbit square memory with 20 address lines would output 2 / 4 / 8 / 16 / 32 / 64
bits of data in a given read. The row decoder would have _________ inputs while the
MUX selector would have _________ inputs.
b) Say the value in R1 is 0x100000. Using the addi assembly instruction to add to R1,
the result of the command would be in the range of 0x __________________ to
0x ___________________.
c) Using a code with a Hamming distance of 6 the largest number of errors you can
correct is _______. If all you were doing is error detection with this code you
could detect up to ________ bits of error.
d) When using a PowerPC823 bus running at 10MHz, the fastest you could read data
from memory is __________________ bytes/sec without burst transactions and
__________________ bytes/sec with burst transactions.
e) The hold time of a circuit is the time before / after the rising edge of the clock that the
data must be held constant.
f) A leaf function is a function that doesn’t __________________________________.
g) The generic term “ caller save register” is the same as a volatile / non-volatile register in our ABI specification.
h) If R1 holds the value 0xF0F0F0F0, then the instruction: andis r1, r1, (0xFF0000FF)@l
would result in R1 having a value of 0x ________________________
a) What is the value of SIVEC? Show your work [2]
b) Which interrupts, if any, would be cleared if you wrote 0xFFFF to SIPEND? [3]
Simple pedometers work by counting the strides of a walker. A simple inertial sensor consisting of a spring and weight produces a pulse each time the walker accelerates thru a stride. The pulses are counted and displayed to get a relative idea of distance traveled. Simple pedometers like this are manually calibrated by adjusting the response of the sensor.
An eccentric friend studying exercise physiology has recently discovered that the time between strides roughly corresponds to distance traveled in a stride. You scheme to get rich quick by designing a pedometer that does not require calibration. To test the idea, let’s assume you have access to a mobile version of the lab kit, a digital display and an inertial sensor that produces a 10s, active high, pulse for each stride.
Further, it turns out that the lab kit does not provide access to the “TIN” pin. As such, using the capture functionality of the PPC823’s timers isn’t a viable option. However, as this will be the only interrupt in the system and the frequency of the inputs is so low compared to the processor speed, the task can be done by directly reading the count register.
Complete or answer the following design questions.
Part 1 (4 points) The physiologist reports that stride distance roughly correlates to 16ms per tenth of a foot. We reason that we can measure the time by interrupting on each stride pulse and using general-purpose timer1 to measure the time between pulses.
To provide enough accuracy, we want to measure with a 1ms resolution. To accommodate the slower clock rate, a slower system clock running at 2.4Mhz is provided rather then the 24Mhz clock we use in lab.
What fields in the timer1 mode register will you program to provide a count resolution of 1ms in the timer1 count register and what are the values of those fields? Do not be concerned about other control features of the counter.
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Part 3 (15 points) Write an interrupt handler at 0x500 to accumulate and display the result in tenths of a foot. You can assume the following:
Suggestions and restrictions: Provide high-level descriptions or comments for your code. For example, Create stack frame Save registers Etc
Excessive stack or register usage will result in a loss of points, as will highly inelegant code. The next page is left blank for your answer if there is not enough room below.
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Part 3 (space for answer)
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Part 5 (15 points) Design the logic required for the signal generation of TA* and Latch. Assume the following hierarchical connections are available and labeled A[6..11], RW, CLK and TS. You may use standard logic elements or Verilog. To improve your chances of scoring, be neat and clear.