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Question Points Score 1 3 2 5 3^9 4 9 5 12 6 12 7 50 8 50 9 50 Total 200
Questions 1-6 are short answer. Only the first two sentences of each part will be graded.
- (3 pts) On PowerPC processors, as on all RISC architectures, loading an arbitrary 32-bit constant into a register requires two instructions. Why doesn’t PowerPC have a single instruction that loads a 32-bit immediate value?
- (5 pts) ABI
a) What is the purpose of an application binary interface (ABI)?
b) An ABI must specify several things to fulfill its purpose; for example, which register is used as the stack pointer. Name three other things specified by an ABI.
- (9 pts) Memory types: You’re designing a new digital set-top box for a next-generation high- definition cable TV system. For each of the data types listed, recommend a type of memory and list the key features of that memory type that make it the best choice for that application.
a) Instructions (text segment): needs to be easily upgradable, at least 1 Mbyte
b) Non-volatile storage for channel, volume, etc. settings, so that the device powers up in the same state as when it was powered off (less than 256 bytes)
c) Video buffer for real-time special effects: at least 32 Mbytes, can be volatile
- (12 pts) Busses & Interrupts a) What is a split-transaction bus?
b) Is the MPC823 bus asynchronous, semi-synchronous, or synchronous?
c) When an interrupt occurs in a system with true vectored interrupts, how is the interrupting device identified? List the primary advantage and primary disadvantage of this technique.
d) If multiple devices generate interrupts simultaneously on a system with non-vectored interrupts, what determines which device will get serviced first?
- Bus operation. a) The diagram below shows several cycles of activity on the MPC823 bus. The vertical dashed lines indicate the successive rising clock edges on which the bus signals are sampled. For each cycle, briefly describe what (if anything) is happening on that cycle.
Cycle Description C
C
C
C
C
C
C
C
C
BR1*
BG0*
BG1*
BB*
TS*
TA*
A[0:31]
D[0:31]
R/W*
BR0*
A1 A
D1 D
C0 C1 C2 C3 C4 C5 C6 C7 C
- For this problem, you will design a simple SRAM-based memory system for the MPC823. Refer to the problem 9a for an MPC823 bus timing diagram.
a) Your first task is to design a module that takes the transaction size control signals and the low-order address bits and generates high-true byte enables. The logic symbol for the module and the definition of the transaction-size signals TSIZ[0:1] are given below. Follow the PowerPC convention that bit 0 is the most significant bit of each bus. Complete the truth table.
TSIZ[0:1] Access Size 00 Word 01 Byte 10 Halfword 11 Unused
TSIZ0 TSIZ1 A0 A1 BE0 BE1 BE2 BE 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 X X X X X X
b) Draw the logic symbol for a standard 8Kx8 SRAM device. Clearly indicate the width of all busses.
TSIZ[0:1]
A[0:1]
BE[0:3]
c) Using your module from part (a), 8Kx8 SRAMs from part (b), and standard logic gates as needed, build a 64 Kbyte memory for the MPC823 occupying a contiguous region of address space starting at address 0x00180000.
f) How would your byte-enable module from part (a) change if the data bus was 64 bits wide instead of 32 bits wide? Assume that the unused TSIZ code of ‘11’ indicates a 64-bit (doubleword) access. Draw the new logic symbol and describe how the internal logic would change. You don’t need to do a full truth table.
- Nate’s question
