Active High External - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this exam paper are: Active High External, Art of the State, Computer Engineering, Implement Transparent, Transparent Latch, Transparent Latches, Label the Inputs, Toggle Cell, Latch and Mux, Active Low

Typology: Exams

2012/2013

Uploaded on 04/08/2013

seema_852
seema_852 🇮🇳

3.6

(7)

87 documents

1 / 4

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
ECE 2030 Computer Engineering Fall 1999
5 problems, 4 pages Final Exam Solution 13 December 1999
1
Problem 1 (3 parts, 30 points) Art of the State
Part A (10 points) Implement a transparent latch using only six two-input NOR gates. Label the
inputs In and En, and the output Out. No other gates should be used.
Part B (8 points) Implement register with write enable using transparent latches, NAND gates,
and inverters. Use an icon for the transparent latches. Label the inputs In, WE, Φ
ΦΦ
Φ1, Φ
ΦΦ
Φ2 and the
output Out.
Part C (10 points) Assume the following signals are applied to your register. Draw the output
signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.
Φ1
Φ2
WE
In
Out
Problem 2 (2 parts, 20 points) Counters
Part A (10 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and
an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle
pf3
pf4

Partial preview of the text

Download Active High External - Computer Engineering - Solved Exam and more Exams Computer Science in PDF only on Docsity!

5 problems, 4 pages Final Exam Solution 13 December 1999

Problem 1 (3 parts, 30 points) Art of the State

Part A (10 points) Implement a transparent latch using only six two-input NOR gates. Label the

inputs In and En , and the output Out. No other gates should be used.

Part B (8 points) Implement register with write enable using transparent latches, NAND gates,

and inverters. Use an icon for the transparent latches. Label the inputs In , WE, ΦΦΦΦ 1 , ΦΦΦΦ 2 and the

output Out.

Part C (10 points) Assume the following signals are applied to your register. Draw the output

signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.

WE

In

Out

Problem 2 (2 parts, 20 points) Counters

Part A (10 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and

an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle

5 problems, 4 pages Final Exam Solution 13 December 1999

enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output

Out. The - Clear signal has precedence over TE. Label all signals.

Part B (10 points) Now combine three of these toggle cells to build a divide by eight counter.

Your counter should have an active high external clear, active high external count enable, and

three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you

require. Assume clock inputs to the toggle cells are already connected.

Problem 3 (1 part, 10 points) Simplification

Part A (10 points) For the following expression, derive a simplified product of sums expression

using a Karnaugh Map. Circle and list the prime implicants, indicating which are essential.

Then write the simplified POS expression.

F = AB + BCD + BC + C D

5 problems, 4 pages Final Exam Solution 13 December 1999

Problem 5 (1 part, 30 points) The Microcode Problem

Suppose memory location 0x1000 contains two packed, unsigned 16 bit values (one in the upper

sixteen bits, one in the lower 16 bits). Using the datapath on the next page, write a microcode

fragment that computes the average of these two values and stores it (unpacked) back into

memory location 0x1000. Express all values in hexadecimal notation. Use ‘X’ when a value is

don’t cared. For maximum credit, complete the description field. Use only registers 1, 2, and 3.

# X Y Z r we

im en

im va au en

-a /s

lu en

lf su en

st ld en

st en

r/ -w

m sel

description

1 X X 1 1 1 1000 0 X 1 C 0 X 0 0 X 0 r1 <- 1000

2 1 X 2 1 0 X 0 X 0 X 0 X 1 0 1 1 r2 <- [r1]

3 2 X 3 1 1 0010 0 X 0 X 1 0 0 0 X 0 r3 <- r2 >> 16

4 2 X 2 1 1 FFFF 0 X 1 8 0 X 0 0 X 0 r2 <- r2 & FFFF

5 2 3 2 1 0 X 1 0 0 X 0 X 0 0 X 0 r2 <- r2 + r

6 2 X 2 1 1 0001 0 X 0 X 1 1 0 0 X 0 r2 <- r2 / 2

7 1 2 X 0 0 X 0 X 0 X 0 X 0 1 0 1 [r1] <- r