Advanced Bus Techniques - Lecture Notes | EECS 373, Study notes of Electrical and Electronics Engineering

Material Type: Notes; Class: Des Microproc Syst; Subject: Electrical Engineering And Computer Science; University: University of Michigan - Ann Arbor; Term: Winter 1998;

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EECS 373 F98 Notes 10-1 © 1998 Steven K. Reinhardt
Advanced Bus Techniques
How to make busses work more efficiently:
Burst transfers
Pipelining
Split transactions
Burst Transfers
First cycle of every MPC823 bus transaction transfers
address; minimum transaction is two cycles
This limits data transfers to one word every other cycle
We can beat this limit by transferring multiple words in one
transaction using one address cycle:
(Some additional control signals are required, not shown in the
diagram.)
What fraction of bus cycles can we transfer data on now?
CLK
A[6:31]
D[0:31]
RD/WR
TS
A0
D1 D2?? ??
?? ??
?? ??
TA
D0 D3
pf3
pf4

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Advanced Bus Techniques

How to make busses work more efficiently:

  • Burst transfers
  • Pipelining
  • Split transactions

Burst Transfers

  • First cycle of every MPC823 bus transaction transfers address; minimum transaction is two cycles
  • This limits data transfers to one word every other cycle
  • We can beat this limit by transferring multiple words in one transaction using one address cycle:

(Some additional control signals are required, not shown in the diagram.)

  • What fraction of bus cycles can we transfer data on now?

CLK

A[6:31]

D[0:31]

RD/WR

TS

A ?? D1 D2 ??

?? ??

?? ??

TA

D0 D

Burst Transfers (cont’d)

  • What addresses are used for additional data words?
  • Where do burst requests come from?
  • How are burst transfers initiated?
  • MPC823 has two primary signals:
    • BURST: from master: I want to do burst
    • BI: from slave: I can’t do bursts (823 will convert to regular “single-beat” requests)
    • Only 16-byte (4-word) bursts supported, so no need to indicate specific size

MPC823 Burst Transfer Example

  • Slave can hold TA asserted on adjacent cycles (no need to deassert as in previous example)
  • Slave can still insert wait states by not asserting TA
  • BDIP: from master: I still expect another word (simplifies slave control)

CLK

A[6:31]

D[0:31]

RD/WR

TS

A ?? D1 D2 ??

?? ??

?? ??

TA

D0 D

BURST

BDIP

BI

??

Address/Data Multiplexing

  • Pipelining takes advantage of the fact that one transaction does not use both address & data busses at the same time.
  • If the goal is to reduce cost (not increase performance), how might we exploit this fact differently?

Split Transactions

  • Back to high performance... what happens on a pipelined bus when a transaction requires wait states?
  • A split-transaction bus splits each transaction into two largely independent parts, a request (address part) and a reply (data part for reads). Replies may appear in any order.
  • Just as masters arbitrate to initiate a transaction on the address bus, slaves must now arbitrate to put their reply on the data bus.
  • Advantage:
  • Disadvantages:

ADDR

DATA

A1 A2 A3 A

D1 (^) wait?? D3 D4 D state