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ECE 474a/575a Susan Lysecky
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ECE 474A/57A
Computer-Aided Logic Design
Lecture 16
Course Summary and More Topics
ECE 474a/575a Susan Lysecky
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What Have We Done?
ze
Design Specification
Structural vs. Behavioral Design and implementation of sequential circuits – RTL (Register-Transfer Level) Design C to gates
Optimization Techniques
Optimization and tradeoffs of combinational and sequential circuits Heuristic minimization of two-level circuits Binary decision diagrams (BDDs)
Multi-Level Minimization
CAD Tools
Utilize industry standard tools to simulate (and synthesize) design Develop optimization tools
ECE 474a/575a Susan Lysecky
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Is That All There Is?
Structural
Physical
Behavioral
System Specification Algorithm Register-Transfer
CPU, Memory Controller, Net-list ALU, Register, Memory Gate, Flip-flop
Cell Layout
Standard Cell
Modules
Block/Chip
Algorithmic Level
Register Transfer Level
Logic Level
Circuit Level
System Level
Boards
Transistor Function Transistor
Boolean Equation
Remember the Y-chart
Design tasks can be performed at different abstractions
Topics we studied are no different
Design Specification Optimization Techniques CAD Tools
We looked at quite a few, but much
more exists
ECE 474a/575a Susan Lysecky
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Algorithm Selection
0x
0x
2: 0x0000000F
256x32 memory
Linear
search
Binary
search
Chosen algorithm can have big impact
Example: Quickly find item’s address in 256-
word memory
Algorithm 1: “Linear search” Compare item with M[0], then M[1], M[2], ... 256 comparisons worst case Algorithm 2: “Binary search” (sort memory first) Start considering entire memory range If M[mid]>item, consider lower half of M If M[mid]<item, consider upper half of M Repeat on new smaller range Dividing range by 2 each step; at most 8 such divisions Only 8 comparisons in worst case
Choice of algorithm hastremendous impact
Far more impact than say choice of comparator type Research looks at how to write algorithm intended to run of HW vs. SW
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
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Pipelining
W1 D1 W2 D2 W3D
Without pipelining:
With pipelining:
“Stage 1”
“Stage 2”
Time
W
D
W
D
W
D
a
Intuitive example: Washing dishes with a
friend, you wash, friend dries
You wash plate 1
Then friend dries plate 1,while you wash
plate 2
Then friend dries plate 2, while you wash plate 3; and so on You don’t sit and watch friend dry; you start on the next plate
Pipelining: Break task into stages, each
stage outputs data for next stage, all stages
operate concurrently (if they have data)
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
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Concurrency
Concurrency : Divide task into subparts,
execute subparts simultaneously
Dishwashing example: Divide stack into 3 substacks, give substacks to 3 neighbors, who work simultaneously -- 3 times speedup (ignoring time to move dishes to neighbors' homes) Concurrency does things side-by-side; pipelining instead uses stages (like a factory line)
Task
Concurrency Pipelining
Can do both, too
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
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Power Optimization
Low-Power Gates on Non-Critical Paths
Another method: Use low-power gates
Multiple versions of gates may exist Fast/high-power, and slow/low-power, versions Use slow/low-power gates on non-critical paths Reduces power, without increasing delay
g
f
e
d
c
a b
F
26 transistors 3 ns delay 5 nanowatts power
nanowatts nanoseconds (^) gf
e
d
c
a b
F
26 transistors 3 ns delay 4 nanowatts power
low-power gates delay
high-power gates low-power gates on non-critical path
size
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
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Multi-level Logic Optimization Factoring
Logic equation in a form with more than two levels of logic
Many instances when smaller input gates require less are and power
out = af’c + af’de + bgc + bgde
out
af’
a f’c
ed
bg
bg c
ed
f = af’c + af’de + bgc + bgde f = af’(c + de) + bg(c + de) f = (af’ + bg)(c + de)
f = (af’ + bg)(c + de)
c d e
b g
a f’
f
out = af’c + af’de + bgc + bgde
out
af’
af’ c
ed
bg
b gc
ed
f = af’c + af’de + bgc + bgde f = af’(c + de) + bg(c + de) f = (af’ + bg)(c + de)
f = (af’ + bg)(c + de)
c d e
b g
a f’
f
12a. x · (y + z) = xy + xz 12b. x + y · z = (x+y) · (x+z)
ECE 474a/575a Susan Lysecky
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Multi-level Logic Optimization
Functional Decomposition
Functional Decomposition
Replace two-level logic equation with two or more new expressions which are then combined to define multilevel circuit
F = x1’x2x3 + x1x2’x3 + x1x2x4 + x1’x2’x
F = gx3 + g’x
g = x1’x2 + x1x2’
F
x
x1’ x
x
x x2’
x
x x
x
x1’x2’
x
x
x x2’
x1’ x f cost = 5 + 16 = 21
cost = 6 + 12 = 18
delay = 2 gate-delay
delay = 4 gate-delay
original equation
functional decomposition
F = x1’x2x3 + x1x2’x3 + x1x2x4 + x1’x2’x F = (x1’x2 + x1x2’)x3 + (x1x2 + x1’x2’)x
F = gx3 + g’x4 Re-write the equation using g
Let g(x1, x2) = x1’x2 + x1x2’
g’ = x1x2 + x1’x2’ (^) Observe g’
